/*  ============================================================================
 *   Copyright (c) Texas Instruments Incorporated 2012-2018
 * 
 *  Redistribution and use in source and binary forms, with or without 
 *  modification, are permitted provided that the following conditions 
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright 
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the 
 *    documentation and/or other materials provided with the   
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
*/

/*********************************************************************
* file: cslr_wiz8b8sb.h
*
* Brief: This file contains the Register Description for wiz8b8sb
*
*********************************************************************/
#ifndef CSLR_WIZ8B8SB_H
#define CSLR_WIZ8B8SB_H

#include <ti/csl/cslr.h>
#include <ti/csl/tistdtypes.h>

#ifdef __cplusplus
extern "C" {
#endif

/* Minimum unit = 1 byte */

/**************************************************************************\
* Register Overlay Structure for cmu
\**************************************************************************/
typedef struct  {
    volatile Uint32 CMU_000;
    volatile Uint32 CMU_004;
    volatile Uint32 CMU_008;
    volatile Uint32 CMU_00C;
    volatile Uint32 CMU_010;
    volatile Uint32 CMU_014;
    volatile Uint32 CMU_018;
    volatile Uint32 CMU_01C;
    volatile Uint32 CMU_020;
    volatile Uint32 CMU_024;
    volatile Uint32 CMU_028;
    volatile Uint32 CMU_02C;
    volatile Uint32 CMU_030;
    volatile Uint32 CMU_034;
    volatile Uint32 CMU_038;
    volatile Uint32 CMU_03C;
    volatile Uint32 CMU_040;
    volatile Uint32 CMU_044;
    volatile Uint32 CMU_048;
    volatile Uint32 CMU_04C;
    volatile Uint32 CMU_050;
    volatile Uint32 CMU_054;
    volatile Uint32 CMU_058;
    volatile Uint32 CMU_05C;
    volatile Uint32 CMU_060;
    volatile Uint32 CMU_064;
    volatile Uint32 CMU_068;
    volatile Uint32 CMU_06C;
    volatile Uint32 CMU_070;
    volatile Uint32 CMU_074;
    volatile Uint32 CMU_078;
    volatile Uint32 CMU_07C;
    volatile Uint8 RSVD0[108];
    volatile Uint32 CMU_0EC;
    volatile Uint8 RSVD1[12];
    volatile Uint32 CMU_0FC;
    volatile Uint8 RSVD2[256];
} CSL_Wiz8b8sbCmuRegs;

/**************************************************************************\
* Register Overlay Structure for lane
\**************************************************************************/
typedef struct  {
    volatile Uint32 LANE_000;
    volatile Uint32 LANE_004;
    volatile Uint32 LANE_008;
    volatile Uint32 LANE_00C;
    volatile Uint32 LANE_010;
    volatile Uint32 LANE_014;
    volatile Uint32 LANE_018;
    volatile Uint32 LANE_01C;
    volatile Uint32 LANE_020;
    volatile Uint32 LANE_024;
    volatile Uint32 LANE_028;
    volatile Uint32 LANE_02C;
    volatile Uint32 LANE_030;
    volatile Uint32 LANE_034;
    volatile Uint32 LANE_038;
    volatile Uint32 LANE_03C;
    volatile Uint32 LANE_040;
    volatile Uint32 LANE_044;
    volatile Uint32 LANE_048;
    volatile Uint32 LANE_04C;
    volatile Uint32 LANE_050;
    volatile Uint32 LANE_054;
    volatile Uint32 LANE_058;
    volatile Uint32 LANE_05C;
    volatile Uint32 LANE_060;
    volatile Uint8 RSVD0[20];
    volatile Uint32 LANE_078;
    volatile Uint32 LANE_07C;
    volatile Uint32 LANE_080;
    volatile Uint32 LANE_084;
    volatile Uint32 LANE_088;
    volatile Uint32 LANE_08C;
    volatile Uint32 LANE_090;
    volatile Uint32 LANE_094;
    volatile Uint32 LANE_098;
    volatile Uint32 LANE_09C;
    volatile Uint32 LANE_0A0;
    volatile Uint32 LANE_0A4;
    volatile Uint32 LANE_0A8;
    volatile Uint32 LANE_0AC;
    volatile Uint32 LANE_0B0;
    volatile Uint32 LANE_0B4;
    volatile Uint32 LANE_0B8;
    volatile Uint8 RSVD1[324];
} CSL_Wiz8b8sbLaneRegs;

/**************************************************************************\
* Register Overlay Structure for comlane
\**************************************************************************/
typedef struct  {
    volatile Uint32 COMLANE_000;
    volatile Uint32 COMLANE_004;
    volatile Uint32 COMLANE_008;
    volatile Uint32 COMLANE_00C;
    volatile Uint32 COMLANE_010;
    volatile Uint32 COMLANE_014;
    volatile Uint32 COMLANE_018;
    volatile Uint32 COMLANE_01C;
    volatile Uint8 RSVD0[16];
    volatile Uint32 COMLANE_030;
    volatile Uint32 COMLANE_034;
    volatile Uint32 COMLANE_038;
    volatile Uint32 COMLANE_03C;
    volatile Uint32 COMLANE_040;
    volatile Uint32 COMLANE_044;
    volatile Uint32 COMLANE_048;
    volatile Uint32 COMLANE_04C;
    volatile Uint32 COMLANE_050;
    volatile Uint32 COMLANE_054;
    volatile Uint32 COMLANE_058;
    volatile Uint32 COMLANE_05C;
    volatile Uint32 COMLANE_060;
    volatile Uint32 COMLANE_064;
    volatile Uint32 COMLANE_068;
    volatile Uint32 COMLANE_06C;
    volatile Uint32 COMLANE_070;
    volatile Uint32 COMLANE_074;
    volatile Uint32 COMLANE_078;
    volatile Uint32 COMLANE_07C;
    volatile Uint32 COMLANE_080;
    volatile Uint32 COMLANE_084;
    volatile Uint32 COMLANE_088;
    volatile Uint32 COMLANE_08C;
    volatile Uint32 COMLANE_090;
    volatile Uint32 COMLANE_094;
    volatile Uint32 COMLANE_098;
    volatile Uint32 COMLANE_09C;
    volatile Uint32 COMLANE_0A0;
    volatile Uint32 COMLANE_0A4;
    volatile Uint32 COMLANE_0A8;
    volatile Uint32 COMLANE_0AC;
    volatile Uint32 COMLANE_0B0;
    volatile Uint32 COMLANE_0B4;
    volatile Uint32 COMLANE_0B8;
    volatile Uint32 COMLANE_0BC;
    volatile Uint32 COMLANE_0C0;
    volatile Uint32 COMLANE_0C4;
    volatile Uint32 COMLANE_0C8;
    volatile Uint8 RSVD1[28];
    volatile Uint32 COMLANE_0E8;
    volatile Uint32 COMLANE_0EC;
    volatile Uint32 COMLANE_0F0;
    volatile Uint32 COMLANE_0F4;
    volatile Uint32 COMLANE_0F8;
    volatile Uint32 COMLANE_0FC;
    volatile Uint32 COMLANE_100;
    volatile Uint32 COMLANE_104;
    volatile Uint32 COMLANE_108;
    volatile Uint32 COMLANE_10C;
    volatile Uint32 COMLANE_110;
    volatile Uint32 COMLANE_114;
    volatile Uint32 COMLANE_118;
    volatile Uint32 COMLANE_11C;
    volatile Uint32 COMLANE_120;
    volatile Uint32 COMLANE_124;
    volatile Uint8 RSVD2[204];
    volatile Uint32 COMLANE_1F4;
    volatile Uint32 COMLANE_1F8;
    volatile Uint32 COMLANE_1FC;
} CSL_Wiz8b8sbComlaneRegs;

/**************************************************************************\
* Register Overlay Structure for config
\**************************************************************************/
typedef struct  {
    volatile Uint32 MOD_VER;
    volatile Uint8 RSVD0[28];
    volatile Uint32 LANEXCTL_STS[4];
    volatile Uint8 RSVD1[4];
    volatile Uint32 PLL_CTRL;
    volatile Uint32 COMMA_LINK_DELAY;
    volatile Uint32 CMU_WAIT;
} CSL_Wiz8b8sbConfigRegs;

/**************************************************************************\
* Register Overlay Structure
\**************************************************************************/
typedef struct  {
    CSL_Wiz8b8sbCmuRegs CMU;
    CSL_Wiz8b8sbLaneRegs LANE[4];
    CSL_Wiz8b8sbComlaneRegs COMLANE;
    volatile Uint8 RSVD0[5056];
    CSL_Wiz8b8sbConfigRegs CONFIG;
} CSL_Wiz8b8sbRegs;

/**************************************************************************\
* Field Definition Macros
\**************************************************************************/

/* cmu_000 */

#define CSL_WIZ8B8SB_CMU_000_SOC1_DIV_O_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_CMU_000_SOC1_DIV_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_CMU_000_SOC1_DIV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_SOC0_DIV_O_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_CMU_000_SOC0_DIV_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_000_SOC0_DIV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_CMU_PD_TXCLK_DIV_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_CMU_000_CMU_PD_TXCLK_DIV_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_CMU_000_CMU_PD_TXCLK_DIV_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_OVR_O_MASK (0x00700000u)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_OVR_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_SSC_EN_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_CMU_000_SSC_EN_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_CMU_000_SSC_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_SSC_GEN_EN_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_CMU_000_SSC_GEN_EN_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_CMU_000_SSC_GEN_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_PCS_RATE_O_MASK (0x00030000u)
#define CSL_WIZ8B8SB_CMU_000_PCS_RATE_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_000_PCS_RATE_O_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_CMU_000_SSC_CLK_DIV_O_MASK (0x0000C000u)
#define CSL_WIZ8B8SB_CMU_000_SSC_CLK_DIV_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_CMU_000_SSC_CLK_DIV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_GCFSM_CLK_DIV_O_MASK (0x00003000u)
#define CSL_WIZ8B8SB_CMU_000_GCFSM_CLK_DIV_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_CMU_000_GCFSM_CLK_DIV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_NUM_CYCLES_O_9_6_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_NUM_CYCLES_O_9_6_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_NUM_CYCLES_O_9_6_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_NUM_CYCLES_O_5_0_MASK (0x000000FCu)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_NUM_CYCLES_O_5_0_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_NUM_CYCLES_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_GOOD_STATE_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_GOOD_STATE_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_CMU_000_PLL_CTRL_GOOD_STATE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_000_CMU_MASTER_CDN_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_CMU_000_CMU_MASTER_CDN_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_000_CMU_MASTER_CDN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_000_RESETVAL    (0x00820802u)

/* cmu_004 */

#define CSL_WIZ8B8SB_CMU_004_SSC_GEN_MATCH_VAL_O_11_4_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_004_SSC_GEN_MATCH_VAL_O_11_4_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_004_SSC_GEN_MATCH_VAL_O_11_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_004_SSC_GEN_MATCH_VAL_O_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_CMU_004_SSC_GEN_MATCH_VAL_O_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_CMU_004_SSC_GEN_MATCH_VAL_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_19_16_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_19_16_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_19_16_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_15_8_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_15_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_004_SSC_FCNTL_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_004_RESETVAL    (0x00000000u)

/* cmu_008 */

#define CSL_WIZ8B8SB_CMU_008_TBUS_ADDR_OVR_O_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_008_TBUS_ADDR_OVR_O_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_008_TBUS_ADDR_OVR_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_INC_VAL_O_15_8_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_INC_VAL_O_15_8_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_INC_VAL_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_INC_VAL_O_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_INC_VAL_O_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_INC_VAL_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_MATCH_VAL_O_19_12_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_MATCH_VAL_O_19_12_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_008_SSC_GEN_MATCH_VAL_O_19_12_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_008_RESETVAL    (0x00000000u)

/* cmu_00c */

#define CSL_WIZ8B8SB_CMU_00C_MSM_OUT_OVR_O_15_8_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_00C_MSM_OUT_OVR_O_15_8_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_00C_MSM_OUT_OVR_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_00C_MSM_OUT_OVR_O_7_0_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_00C_MSM_OUT_OVR_O_7_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_00C_MSM_OUT_OVR_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_00C_AMUX_OVR_O_8_1_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_00C_AMUX_OVR_O_8_1_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_00C_AMUX_OVR_O_8_1_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_00C_AMUX_OVR_O_0_MASK (0x00000040u)
#define CSL_WIZ8B8SB_CMU_00C_AMUX_OVR_O_0_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_CMU_00C_AMUX_OVR_O_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_00C_MSM_IN_OVR_O_5_0_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_CMU_00C_MSM_IN_OVR_O_5_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_00C_MSM_IN_OVR_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_00C_RESETVAL    (0x00000000u)

/* cmu_010 */

#define CSL_WIZ8B8SB_CMU_010_CMU_IN_OVR_O_2_0_MASK (0x70000000u)
#define CSL_WIZ8B8SB_CMU_010_CMU_IN_OVR_O_2_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_CMU_010_CMU_IN_OVR_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_27_24_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_27_24_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_27_24_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_23_16_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_23_16_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_23_16_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_15_8_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_15_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_010_GCFSM_OVR_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_010_RESETVAL    (0x00000000u)

/* cmu_014 */

#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_31_24_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_31_24_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_31_24_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_23_16_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_23_16_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_23_16_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_15_8_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_15_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_15_8_RESETVAL (0x0000002Eu)

#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_014_GCFSM_CYCLE_LEN_O_7_0_RESETVAL (0x0000002Eu)

#define CSL_WIZ8B8SB_CMU_014_RESETVAL    (0x00052E2Eu)

/* cmu_018 */

#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_63_56_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_63_56_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_63_56_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_55_48_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_55_48_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_55_48_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_47_40_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_47_40_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_47_40_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_39_32_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_39_32_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_018_GCFSM_CYCLE_LEN_O_39_32_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_018_RESETVAL    (0x00000000u)

/* cmu_01c */

#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_95_88_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_95_88_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_95_88_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_87_80_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_87_80_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_87_80_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_79_72_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_79_72_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_79_72_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_71_64_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_71_64_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_01C_GCFSM_CYCLE_LEN_O_71_64_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_01C_RESETVAL    (0x00000000u)

/* cmu_020 */

#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_127_120_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_127_120_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_127_120_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_119_112_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_119_112_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_119_112_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_111_104_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_111_104_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_111_104_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_103_96_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_103_96_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_020_GCFSM_CYCLE_LEN_O_103_96_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_020_RESETVAL    (0x00000000u)

/* cmu_024 */

#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_03_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_03_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_03_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_02_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_02_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_02_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_01_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_01_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_01_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_00_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_00_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_024_UNDEFINED_00_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_024_RESETVAL    (0x00000000u)

/* cmu_028 */

#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_07_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_07_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_07_RESETVAL (0x000000A0u)

#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_06_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_06_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_06_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_05_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_05_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_05_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_04_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_04_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_028_UNDEFINED_04_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_028_RESETVAL    (0xA0020000u)

/* cmu_02c */

#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_11_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_11_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_11_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_10_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_10_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_10_RESETVAL (0x00000041u)

#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_09_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_09_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_09_RESETVAL (0x00000044u)

#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_08_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_08_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_02C_UNDEFINED_08_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_CMU_02C_RESETVAL    (0x20414402u)

/* cmu_030 */

#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_15_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_15_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_15_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_14_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_14_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_14_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_13_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_13_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_13_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_12_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_12_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_030_UNDEFINED_12_RESETVAL (0x0000000Cu)

#define CSL_WIZ8B8SB_CMU_030_RESETVAL    (0x0000200Cu)

/* cmu_034 */

#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_19_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_19_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_19_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_18_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_18_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_18_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_17_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_17_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_17_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_16_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_16_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_034_UNDEFINED_16_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_034_RESETVAL    (0x00000000u)

/* cmu_038 */

#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_23_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_23_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_23_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_22_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_22_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_22_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_21_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_21_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_21_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_20_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_20_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_038_UNDEFINED_20_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_038_RESETVAL    (0x00000000u)

/* cmu_03c */

#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_27_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_27_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_27_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_26_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_26_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_26_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_25_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_25_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_25_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_24_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_24_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_03C_UNDEFINED_24_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_03C_RESETVAL    (0x00000000u)

/* cmu_040 */

#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_31_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_31_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_31_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_30_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_30_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_30_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_29_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_29_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_29_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_28_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_28_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_040_UNDEFINED_28_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_040_RESETVAL    (0x00000000u)

/* cmu_044 */

#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_35_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_35_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_35_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_34_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_34_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_34_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_33_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_33_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_33_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_32_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_32_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_044_UNDEFINED_32_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_044_RESETVAL    (0x00000000u)

/* cmu_048 */

#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_39_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_39_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_39_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_38_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_38_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_38_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_37_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_37_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_37_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_36_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_36_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_048_UNDEFINED_36_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_048_RESETVAL    (0x00000000u)

/* cmu_04c */

#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_43_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_43_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_43_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_42_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_42_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_42_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_41_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_41_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_41_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_40_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_40_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_04C_UNDEFINED_40_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_04C_RESETVAL    (0x00000000u)

/* cmu_050 */

#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_47_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_47_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_47_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_46_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_46_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_46_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_45_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_45_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_45_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_44_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_44_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_050_UNDEFINED_44_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_050_RESETVAL    (0x00000000u)

/* cmu_054 */

#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_51_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_51_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_51_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_50_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_50_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_50_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_49_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_49_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_49_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_48_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_48_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_054_UNDEFINED_48_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_054_RESETVAL    (0x00000000u)

/* cmu_058 */

#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_55_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_55_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_55_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_54_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_54_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_54_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_53_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_53_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_53_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_52_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_52_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_058_UNDEFINED_52_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_058_RESETVAL    (0x00000000u)

/* cmu_05c */

#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_59_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_59_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_59_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_58_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_58_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_58_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_57_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_57_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_57_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_56_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_56_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_05C_UNDEFINED_56_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_05C_RESETVAL    (0x00000000u)

/* cmu_060 */

#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_63_MASK (0x80000000u)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_63_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_63_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FORCE_ILF_MASK (0x60000000u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FORCE_ILF_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FORCE_ILF_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_VCOFR_MASK (0x1C000000u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_VCOFR_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_VCOFR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_62_MASK (0x03000000u)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_62_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_62_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_61_MASK (0x00800000u)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_61_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_61_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_I_KVCO_SEL_MASK (0x00600000u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_I_KVCO_SEL_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_I_KVCO_SEL_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_PREDIV4_ENA_MASK (0x00100000u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_PREDIV4_ENA_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_PREDIV4_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_PLL_REFDIV2_ENA_MASK (0x00080000u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_PLL_REFDIV2_ENA_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_PLL_REFDIV2_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FL_LDHS_A_MASK (0x00070000u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FL_LDHS_A_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FL_LDHS_A_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FL_LDHS_MASK (0x0000FE00u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FL_LDHS_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_FL_LDHS_RESETVAL (0x00000073u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_DIVNSEL_A_MASK (0x00000100u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_DIVNSEL_A_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_DIVNSEL_A_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_PMA_CM_DIVNSEL_MASK (0x000000FCu)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_DIVNSEL_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_CMU_060_PMA_CM_DIVNSEL_RESETVAL (0x00000012u)

#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_60_MASK (0x00000003u)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_60_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_060_UNDEFINED_60_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_060_RESETVAL    (0x0044E648u)

/* cmu_064 */

#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_66_MASK (0xE0000000u)
#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_66_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_66_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_PFD_FORCE_UP_MASK (0x10000000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_PFD_FORCE_UP_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_PFD_FORCE_UP_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_PFD_FORCE_DN_MASK (0x08000000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_PFD_FORCE_DN_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_PFD_FORCE_DN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREGH_MASK (0x06000000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREGH_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREGH_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREG_A_MASK (0x01000000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREG_A_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREG_A_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREG_MASK (0x00800000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREG_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VREG_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VCO_BIAS_MASK (0x00780000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VCO_BIAS_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_VCO_BIAS_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_BGSTART_BYP_MASK (0x00040000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_BGSTART_BYP_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_BGSTART_BYP_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CAP_SEL_A_MASK (0x00030000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CAP_SEL_A_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CAP_SEL_A_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CAP_SEL_MASK (0x00008000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CAP_SEL_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CAP_SEL_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_CHPMP_CHOP_ENAN_MASK (0x00004000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_CHPMP_CHOP_ENAN_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_CHPMP_CHOP_ENAN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_LFI_EXTZERO_MASK (0x00002000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_LFI_EXTZERO_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_LFI_EXTZERO_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_LF_EXTZERO_ENA_MASK (0x00001000u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_LF_EXTZERO_ENA_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_LF_EXTZERO_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_P_CAP_SEL_MASK (0x00000E00u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_P_CAP_SEL_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_P_CAP_SEL_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_C1_SEL_MASK (0x00000100u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_C1_SEL_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_C1_SEL_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_65_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_65_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_65_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_HIZ_MASK (0x00000008u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_HIZ_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_HIZ_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CP_SEL_MASK (0x00000006u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CP_SEL_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_CMU_064_PMA_CM_I_CP_SEL_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_64_MASK (0x00000001u)
#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_64_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_064_UNDEFINED_64_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_064_RESETVAL    (0x02C18702u)

/* cmu_068 */

#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_71_MASK (0x80000000u)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_71_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_71_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_068_PMA_CM_DIVPSEL_MASK (0x7F000000u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_DIVPSEL_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_DIVPSEL_RESETVAL (0x00000017u)

#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_70_MASK (0x00C00000u)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_70_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_70_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_068_PMA_CM_I_DROPI_MASK (0x00200000u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_I_DROPI_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_I_DROPI_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_068_PMA_CM_PFD_PW_MASK (0x00180000u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_PFD_PW_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_PFD_PW_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_068_PMA_CM_AFE_CNTL_A_MASK (0x00070000u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_AFE_CNTL_A_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_AFE_CNTL_A_RESETVAL (0x00000007u)

#define CSL_WIZ8B8SB_CMU_068_PMA_CM_AFE_CNTL_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_AFE_CNTL_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_AFE_CNTL_RESETVAL (0x00000010u)

#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_69_MASK (0x00000400u)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_69_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_69_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_068_PMA_CM_PCS_CLK_ENA_MASK (0x00000200u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_PCS_CLK_ENA_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_CMU_068_PMA_CM_PCS_CLK_ENA_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_68_MASK (0x00000100u)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_68_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_68_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_67_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_67_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_068_UNDEFINED_67_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_068_RESETVAL    (0x170F8200u)

/* cmu_06c */

#define CSL_WIZ8B8SB_CMU_06C_GCFSM_CMU_PMA_DATA_OVR_O_6_0_MASK (0xFE000000u)
#define CSL_WIZ8B8SB_CMU_06C_GCFSM_CMU_PMA_DATA_OVR_O_6_0_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_CMU_06C_GCFSM_CMU_PMA_DATA_OVR_O_6_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_GCFSM_CMU_OUT_OVR_EN_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_CMU_06C_GCFSM_CMU_OUT_OVR_EN_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_06C_GCFSM_CMU_OUT_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_CMU_OUT_OVR_O_1_0_MASK (0x00300000u)
#define CSL_WIZ8B8SB_CMU_06C_CMU_OUT_OVR_O_1_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_CMU_06C_CMU_OUT_OVR_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_TBUS_HOLD_MASK (0x00080000u)
#define CSL_WIZ8B8SB_CMU_06C_TBUS_HOLD_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_CMU_06C_TBUS_HOLD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_CK_SOC_DIV_OVR_O_2_0_MASK (0x00070000u)
#define CSL_WIZ8B8SB_CMU_06C_CK_SOC_DIV_OVR_O_2_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_06C_CK_SOC_DIV_OVR_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_PMA_REFCLK_SEL_OVR_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_CMU_06C_PMA_REFCLK_SEL_OVR_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_CMU_06C_PMA_REFCLK_SEL_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_CDR_REFDIV_O_1_0_MASK (0x00006000u)
#define CSL_WIZ8B8SB_CMU_06C_CDR_REFDIV_O_1_0_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_CMU_06C_CDR_REFDIV_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_CDR_REFCLK_SEL_O_1_0_MASK (0x00001800u)
#define CSL_WIZ8B8SB_CMU_06C_CDR_REFCLK_SEL_O_1_0_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_CMU_06C_CDR_REFCLK_SEL_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_PMA_REFCLK_INPUT_SEL_O_2_0_MASK (0x00000700u)
#define CSL_WIZ8B8SB_CMU_06C_PMA_REFCLK_INPUT_SEL_O_2_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_06C_PMA_REFCLK_INPUT_SEL_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_SSC_GEN_UPDOWN_EN_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_CMU_06C_SSC_GEN_UPDOWN_EN_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_CMU_06C_SSC_GEN_UPDOWN_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_SSC_GEN_FRACSYN_EN_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_CMU_06C_SSC_GEN_FRACSYN_EN_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_CMU_06C_SSC_GEN_FRACSYN_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_PMA_CM_P_KVCO_SEL_MASK (0x0000003Eu)
#define CSL_WIZ8B8SB_CMU_06C_PMA_CM_P_KVCO_SEL_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_CMU_06C_PMA_CM_P_KVCO_SEL_RESETVAL (0x0000000Au)

#define CSL_WIZ8B8SB_CMU_06C_UNDEFINED_72_MASK (0x00000001u)
#define CSL_WIZ8B8SB_CMU_06C_UNDEFINED_72_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_06C_UNDEFINED_72_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_06C_RESETVAL    (0x00000014u)

/* cmu_070 */

#define CSL_WIZ8B8SB_CMU_070_PMA_RXCLK_OE_R_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_CMU_070_PMA_RXCLK_OE_R_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_CMU_070_PMA_RXCLK_OE_R_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_PMA_RXCLK_OE_L_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_CMU_070_PMA_RXCLK_OE_L_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_CMU_070_PMA_RXCLK_OE_L_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OE_R_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OE_R_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OE_R_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OE_L_O_MASK (0x10000000u)
#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OE_L_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OE_L_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OUTPUT_SEL_O_3_0_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OUTPUT_SEL_O_3_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_070_PMA_REFCLK_OUTPUT_SEL_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_CAL_OVR_O_15_8_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_CAL_OVR_O_15_8_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_CAL_OVR_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_CAL_OVR_O_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_CAL_OVR_O_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_CAL_OVR_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_READ_OVR_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_READ_OVR_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_READ_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_GO_OVR_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_GO_OVR_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_GO_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_LATCH_OVR_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_LATCH_OVR_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_LATCH_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_DATA_OVR_O_11_7_MASK (0x0000001Fu)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_DATA_OVR_O_11_7_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_070_GCFSM_CMU_PMA_DATA_OVR_O_11_7_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_070_RESETVAL    (0x00000000u)

/* cmu_074 */

#define CSL_WIZ8B8SB_CMU_074_AHB_RX_TC_WAIT_NEXT_SAMPLE_MASK (0x70000000u)
#define CSL_WIZ8B8SB_CMU_074_AHB_RX_TC_WAIT_NEXT_SAMPLE_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_CMU_074_AHB_RX_TC_WAIT_NEXT_SAMPLE_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_CMU_074_AHB_RX_TC_WAIT_NEXT_UP_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_CMU_074_AHB_RX_TC_WAIT_NEXT_UP_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_074_AHB_RX_TC_WAIT_NEXT_UP_RESETVAL (0x0000000Cu)

#define CSL_WIZ8B8SB_CMU_074_PMA_CM_RX_TERM_OVR_O_MASK (0x003E0000u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_RX_TERM_OVR_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_RX_TERM_OVR_O_RESETVAL (0x00000019u)

#define CSL_WIZ8B8SB_CMU_074_PMA_CM_RX_TERM_OVR_EN_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_RX_TERM_OVR_EN_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_RX_TERM_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_074_PMA_CM_REFCLK_TERM_OVR_O_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_REFCLK_TERM_OVR_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_REFCLK_TERM_OVR_O_RESETVAL (0x00000019u)

#define CSL_WIZ8B8SB_CMU_074_PMA_CM_REFCLK_TERM_OVR_EN_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_REFCLK_TERM_OVR_EN_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_REFCLK_TERM_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_074_SOC1_MAC_CLK_DIV_O_MASK (0x00000300u)
#define CSL_WIZ8B8SB_CMU_074_SOC1_MAC_CLK_DIV_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_074_SOC1_MAC_CLK_DIV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_074_PMA_CM_HV2P5SEL_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_HV2P5SEL_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_074_PMA_CM_HV2P5SEL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_074_RESETVAL    (0x1C32C800u)

/* cmu_078 */

#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_MASK (0x7F000000u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_RESETVAL (0x00000040u)

#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_CLK_DIV_O_7_0_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_CLK_DIV_O_7_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_CLK_DIV_O_7_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_OVR_EN_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_OVR_EN_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_OVR_O_4_0_MASK (0x00007C00u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_OVR_O_4_0_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_OVR_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_POLARITY_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_POLARITY_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_POLARITY_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_POLL_EN_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_POLL_EN_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_078_AHB_CMU_TEMP_CAL_POLL_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_078_AHB_RX_TC_BIAS_OVR_MASK (0x000000E0u)
#define CSL_WIZ8B8SB_CMU_078_AHB_RX_TC_BIAS_OVR_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_CMU_078_AHB_RX_TC_BIAS_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_078_AHB_GC_TCCAL_ENA_OVR_MASK (0x00000010u)
#define CSL_WIZ8B8SB_CMU_078_AHB_GC_TCCAL_ENA_OVR_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_CMU_078_AHB_GC_TCCAL_ENA_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_078_AHB_RX_TC_UP_NUM_SAMPLES_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_CMU_078_AHB_RX_TC_UP_NUM_SAMPLES_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_078_AHB_RX_TC_UP_NUM_SAMPLES_RESETVAL (0x00000009u)

#define CSL_WIZ8B8SB_CMU_078_RESETVAL    (0x40020009u)

/* cmu_07c */

#define CSL_WIZ8B8SB_CMU_07C_AHB_RX_TC_WAIT_NEXT_UP_8_4_MASK (0x00001F00u)
#define CSL_WIZ8B8SB_CMU_07C_AHB_RX_TC_WAIT_NEXT_UP_8_4_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_CMU_07C_AHB_RX_TC_WAIT_NEXT_UP_8_4_RESETVAL (0x0000001Cu)

#define CSL_WIZ8B8SB_CMU_07C_EN_FRACN_FRCDIV_MODE_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_CMU_07C_EN_FRACN_FRCDIV_MODE_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_CMU_07C_EN_FRACN_FRCDIV_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_TST_CTRL_O_MASK (0x00000060u)
#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_TST_CTRL_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_TST_CTRL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_TST_IN_O_MASK (0x0000001Eu)
#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_TST_IN_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_TST_IN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_CLK_SEL_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_CLK_SEL_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_07C_FRACN_MOD_CLK_SEL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_07C_RESETVAL    (0x00001C00u)

/* cmu_0ec */

#define CSL_WIZ8B8SB_CMU_0EC_TBUS_DATA_SMPL_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_CMU_0EC_TBUS_DATA_SMPL_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_0EC_TBUS_DATA_SMPL_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_0EC_RESETVAL    (0x00000000u)

/* cmu_0fc */

#define CSL_WIZ8B8SB_CMU_0FC_TBUS_DATA_SMPL_11_8_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_CMU_0FC_TBUS_DATA_SMPL_11_8_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_CMU_0FC_TBUS_DATA_SMPL_11_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_CMU_0FC_RESETVAL    (0x00000000u)

/* lane_000 */

#define CSL_WIZ8B8SB_LANE_000_RXCLK_LB_ENA_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_000_RXCLK_LB_ENA_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_000_RXCLK_LB_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_NES_LB_ENA_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_LANE_000_NES_LB_ENA_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_LANE_000_NES_LB_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_SYM_ALIGN_ALIGN_POS_O_5_0_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_LANE_000_SYM_ALIGN_ALIGN_POS_O_5_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_000_SYM_ALIGN_ALIGN_POS_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_CKTRANS_EN_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_LANE_000_CKTRANS_EN_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_LANE_000_CKTRANS_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_DMUX_TXB_SEL_O_2_0_MASK (0x00700000u)
#define CSL_WIZ8B8SB_LANE_000_DMUX_TXB_SEL_O_2_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_000_DMUX_TXB_SEL_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_REG0_WORD_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_LANE_000_REG0_WORD_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_LANE_000_REG0_WORD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_REG0_BIT_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_LANE_000_REG0_BIT_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_LANE_000_REG0_BIT_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_REG0_POL_O_1_0_MASK (0x00030000u)
#define CSL_WIZ8B8SB_LANE_000_REG0_POL_O_1_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_000_REG0_POL_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_AHB_PMA_TXCLK_SEL_0_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_LANE_000_AHB_PMA_TXCLK_SEL_0_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_000_AHB_PMA_TXCLK_SEL_0_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_FES_LB_ENA_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_LANE_000_FES_LB_ENA_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_LANE_000_FES_LB_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_REG1_WORD_O_MASK (0x00002000u)
#define CSL_WIZ8B8SB_LANE_000_REG1_WORD_O_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_LANE_000_REG1_WORD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_REG1_BIT_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_LANE_000_REG1_BIT_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_000_REG1_BIT_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_REG1_POL_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_LANE_000_REG1_POL_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_000_REG1_POL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_TREG1_WORD_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_LANE_000_TREG1_WORD_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_LANE_000_TREG1_WORD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_TREG1_BIT_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_LANE_000_TREG1_BIT_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_000_TREG1_BIT_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_TREG1_POL_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_000_TREG1_POL_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_000_TREG1_POL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_DMUX_TXA_SEL_O_1_0_MASK (0x000000C0u)
#define CSL_WIZ8B8SB_LANE_000_DMUX_TXA_SEL_O_1_0_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_LANE_000_DMUX_TXA_SEL_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_TREG0_WORD_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_LANE_000_TREG0_WORD_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_LANE_000_TREG0_WORD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_TREG0_BIT_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_LANE_000_TREG0_BIT_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_000_TREG0_BIT_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_TREG0_POL_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_LANE_000_TREG0_POL_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_000_TREG0_POL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_RX_SRC_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_LANE_000_RX_SRC_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_000_RX_SRC_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_RX_CLK_SRC_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANE_000_RX_CLK_SRC_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_000_RX_CLK_SRC_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_000_TX_CLK_SRC_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_000_TX_CLK_SRC_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_000_TX_CLK_SRC_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_000_RESETVAL   (0x00000002u)

/* lane_004 */

#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_PREEM_1LSB_MODE_0_OVR_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_PREEM_1LSB_MODE_0_OVR_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_PREEM_1LSB_MODE_0_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_SLEW_SLD_1_0_OVR_O_MASK (0x60000000u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_SLEW_SLD_1_0_OVR_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_SLEW_SLD_1_0_OVR_O_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_ATT_IN_3_0_OVR_O_MASK (0x1E000000u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_ATT_IN_3_0_OVR_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_ATT_IN_3_0_OVR_O_RESETVAL (0x0000000Au)

#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_SEL_SW_MAP_0_OVR_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_SEL_SW_MAP_0_OVR_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_SEL_SW_MAP_0_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_AHB_PD_TXREG_OVR_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_LANE_004_AHB_PD_TXREG_OVR_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_004_AHB_PD_TXREG_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_AHB_TXREG_BLEED_ENA_OVR_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXREG_BLEED_ENA_OVR_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXREG_BLEED_ENA_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_LP_IDLE_0_OVR_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_LP_IDLE_0_OVR_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_LANE_004_AHB_TXDRV_LP_IDLE_0_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_RXEQ_SIGDET_1_0_MASK (0x00030000u)
#define CSL_WIZ8B8SB_LANE_004_RXEQ_SIGDET_1_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_004_RXEQ_SIGDET_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_LN_OUT_OVR_1_0_MASK (0x00006000u)
#define CSL_WIZ8B8SB_LANE_004_LN_OUT_OVR_1_0_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_LANE_004_LN_OUT_OVR_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_PMA_LN_SD_BWSEL_MASK (0x00001000u)
#define CSL_WIZ8B8SB_LANE_004_PMA_LN_SD_BWSEL_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_004_PMA_LN_SD_BWSEL_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_004_REGP_OVR_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_004_REGP_OVR_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_004_REGP_OVR_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_BCHK_CK_SRC_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_CK_SRC_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_CK_SRC_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_BCHK_SRC_O_1_0_MASK (0x00000060u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_SRC_O_1_0_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_SRC_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_BCHK_CLR_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_CLR_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_CLR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_BCHK_EN_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_EN_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_004_BCHK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_SIGDET_OVR_O_1_0_MASK (0x00000006u)
#define CSL_WIZ8B8SB_LANE_004_SIGDET_OVR_O_1_0_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_004_SIGDET_OVR_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_SOC_CK_EN_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_004_SOC_CK_EN_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_004_SOC_CK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_004_RESETVAL   (0x74001000u)

/* lane_008 */

#define CSL_WIZ8B8SB_LANE_008_TXTERM_CAL_RSEL_MASK (0x00070000u)
#define CSL_WIZ8B8SB_LANE_008_TXTERM_CAL_RSEL_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_008_TXTERM_CAL_RSEL_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_CM_IN_3_0_OVR_O_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_CM_IN_3_0_OVR_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_CM_IN_3_0_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_C2_IN_3_0_OVR_O_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_C2_IN_3_0_OVR_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_C2_IN_3_0_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_SLEW_SLD3F_2_0_OVR_O_MASK (0x000000E0u)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_SLEW_SLD3F_2_0_OVR_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_SLEW_SLD3F_2_0_OVR_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_C1_IN_4_0_OVR_O_MASK (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_C1_IN_4_0_OVR_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_008_AHB_TXDRV_C1_IN_4_0_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_008_RESETVAL   (0x00020020u)

/* lane_00c */

#define CSL_WIZ8B8SB_LANE_00C_PIPE_TXCOWARP_MASK (0x04000000u)
#define CSL_WIZ8B8SB_LANE_00C_PIPE_TXCOWARP_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_LANE_00C_PIPE_TXCOWARP_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_00C_AHB_SYM_ALIGN_BYPASS_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_LANE_00C_AHB_SYM_ALIGN_BYPASS_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_LANE_00C_AHB_SYM_ALIGN_BYPASS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_00C_USB_MODE_MASK (0x01000000u)
#define CSL_WIZ8B8SB_LANE_00C_USB_MODE_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_00C_USB_MODE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_00C_RESETVAL   (0x00000000u)

/* lane_010 */

#define CSL_WIZ8B8SB_LANE_010_UNDEFINED_01_MASK (0xC0000000u)
#define CSL_WIZ8B8SB_LANE_010_UNDEFINED_01_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_LANE_010_UNDEFINED_01_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_010_PMA_LN_AGC_THSEL_MASK (0x38000000u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_AGC_THSEL_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_AGC_THSEL_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_010_PMA_LN_SD_THSEL_MASK (0x07000000u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_SD_THSEL_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_SD_THSEL_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOSTOVR_A_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOSTOVR_A_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOSTOVR_A_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOSTOVR_MASK (0x0000FE00u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOSTOVR_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOSTOVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOST_OVR_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOST_OVR_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_010_PMA_LN_RX_BOOST_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_010_UNDEFINED_00_MASK (0x000000FCu)
#define CSL_WIZ8B8SB_LANE_010_UNDEFINED_00_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_010_UNDEFINED_00_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_LANE_010_SYM_ALIGN_MODE_O_1_0_MASK (0x00000003u)
#define CSL_WIZ8B8SB_LANE_010_SYM_ALIGN_MODE_O_1_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_010_SYM_ALIGN_MODE_O_1_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_LANE_010_RESETVAL   (0x1B000022u)

/* lane_014 */

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_CDR_DVDR_ENA_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_CDR_DVDR_ENA_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_CDR_DVDR_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_CDR_DVDR_MASK (0x7E000000u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_CDR_DVDR_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_CDR_DVDR_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_014_UNDEFINED_02_MASK (0x01000000u)
#define CSL_WIZ8B8SB_LANE_014_UNDEFINED_02_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_014_UNDEFINED_02_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_AFE_CNTL_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_AFE_CNTL_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_AFE_CNTL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_INT_STEP_MASK (0x0000E000u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_INT_STEP_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_INT_STEP_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFL_LDHS_A_MASK (0x00001F00u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFL_LDHS_A_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFL_LDHS_A_RESETVAL (0x00000013u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFL_LDHS_MASK (0x000000F8u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFL_LDHS_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFL_LDHS_RESETVAL (0x00000013u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_DLPF_DIV2_ENA_MASK (0x00000004u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_DLPF_DIV2_ENA_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_DLPF_DIV2_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFORCE_PHD_ENA_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFORCE_PHD_ENA_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXFORCE_PHD_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXUP_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXUP_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_014_PMA_LN_RXUP_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_014_RESETVAL   (0x08003398u)

/* lane_018 */

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXDWN_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXDWN_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXDWN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RX_SELC_MASK (0x70000000u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RX_SELC_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RX_SELC_RESETVAL (0x00000007u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_VREGH_MASK (0x0C000000u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_VREGH_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_VREGH_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_VREG_MASK (0x03000000u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_VREG_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_VREG_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXVCO_BIAS_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXVCO_BIAS_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXVCO_BIAS_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_05_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_05_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_05_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_04_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_04_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_04_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RX_SELR_MASK (0x00000E00u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RX_SELR_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RX_SELR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_03_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_03_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_018_UNDEFINED_03_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXPREDIV4_ENA_MASK (0x00000080u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXPREDIV4_ENA_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXPREDIV4_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXVCOFR_MASK (0x00000070u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXVCOFR_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_RXVCOFR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_018_PMA_LN_BB_STEP_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_BB_STEP_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_018_PMA_LN_BB_STEP_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_018_RESETVAL   (0x75800004u)

/* lane_01c */

#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_23_16_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_23_16_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_23_16_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_15_8_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_15_8_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_01C_GCFSM_OVR_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_01C_CMU_CK_EN_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_LANE_01C_CMU_CK_EN_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_LANE_01C_CMU_CK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_01C_UNDEFINED_07_MASK (0x0000003Cu)
#define CSL_WIZ8B8SB_LANE_01C_UNDEFINED_07_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_01C_UNDEFINED_07_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_01C_PMA_LN_PD_VCO_BUF_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANE_01C_PMA_LN_PD_VCO_BUF_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_01C_PMA_LN_PD_VCO_BUF_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_01C_UNDEFINED_06_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_01C_UNDEFINED_06_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_01C_UNDEFINED_06_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_01C_RESETVAL   (0x00000000u)

/* lane_020 */

#define CSL_WIZ8B8SB_LANE_020_MSM_RATE_OVR_O_2_0_MASK (0xE0000000u)
#define CSL_WIZ8B8SB_LANE_020_MSM_RATE_OVR_O_2_0_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_LANE_020_MSM_RATE_OVR_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_18_14_MASK (0x1F000000u)
#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_18_14_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_18_14_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_13_6_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_13_6_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_13_6_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_5_0_MASK (0x0000FC00u)
#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_5_0_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_LANE_020_MSM_OUT_OVR_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_020_MSM_IN_OVR_O_5_4_MASK (0x00000300u)
#define CSL_WIZ8B8SB_LANE_020_MSM_IN_OVR_O_5_4_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_020_MSM_IN_OVR_O_5_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_020_MSM_IN_OVR_O_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_020_MSM_IN_OVR_O_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_020_MSM_IN_OVR_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_020_GCFSM_OVR_O_27_24_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_020_GCFSM_OVR_O_27_24_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_020_GCFSM_OVR_O_27_24_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_020_RESETVAL   (0x00000000u)

/* lane_024 */

#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_20_13_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_20_13_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_20_13_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_12_5_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_12_5_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_12_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_4_0_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_4_0_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_024_CDR_CTRL_OUT_OVR_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_024_BOOST_MAX_LIMIT_EN_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_024_BOOST_MAX_LIMIT_EN_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_024_BOOST_MAX_LIMIT_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_024_BOOST_MAX_LIMIT_O_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_024_BOOST_MAX_LIMIT_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_024_BOOST_MAX_LIMIT_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_024_MSM_RATE_OVR_O_6_3_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_024_MSM_RATE_OVR_O_6_3_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_024_MSM_RATE_OVR_O_6_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_024_RESETVAL   (0x00000000u)

/* lane_028 */

#define CSL_WIZ8B8SB_LANE_028_MSM_OUT_B_OVR_O_1_0_MASK (0xC0000000u)
#define CSL_WIZ8B8SB_LANE_028_MSM_OUT_B_OVR_O_1_0_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_LANE_028_MSM_OUT_B_OVR_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_14_9_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_14_9_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_14_9_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_8_1_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_8_1_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_8_1_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_0_MASK (0x00008000u)
#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_0_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_028_LN_IN_OVR_O_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_LOCKED_OVR_O_1_0_MASK (0x00006000u)
#define CSL_WIZ8B8SB_LANE_028_LOCKED_OVR_O_1_0_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_LANE_028_LOCKED_OVR_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_RXDET_STATUS_OVR_O_1_0_MASK (0x00001800u)
#define CSL_WIZ8B8SB_LANE_028_RXDET_STATUS_OVR_O_1_0_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_028_RXDET_STATUS_OVR_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_TXDETECTRX_OVR_O_1_0_MASK (0x00000600u)
#define CSL_WIZ8B8SB_LANE_028_TXDETECTRX_OVR_O_1_0_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_028_TXDETECTRX_OVR_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_CDR_CTRL_OUT_OVR_O_29_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_028_CDR_CTRL_OUT_OVR_O_29_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_028_CDR_CTRL_OUT_OVR_O_29_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_CDR_CTRL_OUT_OVR_O_28_21_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_028_CDR_CTRL_OUT_OVR_O_28_21_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_028_CDR_CTRL_OUT_OVR_O_28_21_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_028_RESETVAL   (0x00000000u)

/* lane_02c */

#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_EYE_DLY_O_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_EYE_DLY_O_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_EYE_DLY_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_PHD_ENA_O_1_0_MASK (0x00C00000u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_PHD_ENA_O_1_0_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_PHD_ENA_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_DFE_BW_SCALE_MASK (0x00300000u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_DFE_BW_SCALE_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_DFE_BW_SCALE_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_PD_DFE_BIAS_MASK (0x00080000u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_PD_DFE_BIAS_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_LANE_02C_PMA_LN_PD_DFE_BIAS_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_EN_O_6_4_MASK (0x00070000u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_EN_O_6_4_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_EN_O_6_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_EN_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_EN_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_EN_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_CDR_CONTROL_ATT_CTRL_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_LANE_02C_CDR_CONTROL_ATT_CTRL_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_02C_CDR_CONTROL_ATT_CTRL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LATCH_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LATCH_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LATCH_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_O_6_5_MASK (0x00000300u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_O_6_5_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_O_6_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_O_4_0_MASK (0x000000F8u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_O_4_0_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_LOAD_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_EN_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_EN_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_EN_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_EN_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_02C_RXEQ_WAIT_EN_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_WAIT_EN_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_02C_RXEQ_WAIT_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_02C_RESETVAL   (0x00300003u)

/* lane_030 */

#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_PREAM0_O_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_PREAM0_O_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_PREAM0_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_BIST_RX_CLOCK_ENABLE_MASK (0x00800000u)
#define CSL_WIZ8B8SB_LANE_030_BIST_RX_CLOCK_ENABLE_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_LANE_030_BIST_RX_CLOCK_ENABLE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_BIST_TX_CLOCK_ENABLE_MASK (0x00400000u)
#define CSL_WIZ8B8SB_LANE_030_BIST_TX_CLOCK_ENABLE_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_LANE_030_BIST_TX_CLOCK_ENABLE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_LFSR_LENGTH_O_2_0_MASK (0x00380000u)
#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_LFSR_LENGTH_O_2_0_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_LFSR_LENGTH_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_DATA_MODE_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_DATA_MODE_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_LANE_030_BIST_CHK_DATA_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_BIST_GEN_ERR_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_LANE_030_BIST_GEN_ERR_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_LANE_030_BIST_GEN_ERR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_BIST_GEN_MODE8B_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_LANE_030_BIST_GEN_MODE8B_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_030_BIST_GEN_MODE8B_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_RXEQ_SUPERBST_ENA_OVR_MASK (0x00008000u)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_SUPERBST_ENA_OVR_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_SUPERBST_ENA_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_RXEQ_SUPERBST_AUTOCAL_DIS_MASK (0x00004000u)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_SUPERBST_AUTOCAL_DIS_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_SUPERBST_AUTOCAL_DIS_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_RXEQ_ATT_GAIN_OVR_MASK (0x00003000u)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_ATT_GAIN_OVR_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_ATT_GAIN_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_RXEQ_ATT_GAIN_AUTOCAL_DIS_MASK (0x00000800u)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_ATT_GAIN_AUTOCAL_DIS_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_ATT_GAIN_AUTOCAL_DIS_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_UNDEFINED_08_MASK (0x00000300u)
#define CSL_WIZ8B8SB_LANE_030_UNDEFINED_08_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_030_UNDEFINED_08_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_RXEQ_DFE_CMP_SEL_OVR_O_2_0_MASK (0x000000E0u)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_DFE_CMP_SEL_OVR_O_2_0_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_LANE_030_RXEQ_DFE_CMP_SEL_OVR_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_ENA90_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_ENA90_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_ENA90_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_ENA270_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_ENA270_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_ENA270_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_SGN_RST_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_SGN_RST_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_SGN_RST_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_DLY_O_9_8_MASK (0x00000003u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_DLY_O_9_8_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_030_PMA_LN_EYE_DLY_O_9_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_030_RESETVAL   (0x00000000u)

/* lane_034 */

#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_INSERT_COUNT_O_2_0_MASK (0x70000000u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_INSERT_COUNT_O_2_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_INSERT_COUNT_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_SEND_PREAM_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_SEND_PREAM_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_SEND_PREAM_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_CLK_SEL_O_2_0_MASK (0x07000000u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_CLK_SEL_O_2_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_CLK_SEL_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM1_O_9_8_MASK (0x00030000u)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM1_O_9_8_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM1_O_9_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM1_O_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM1_O_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM1_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_EN_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_EN_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_WORD_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_WORD_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_WORD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_CDN_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_CDN_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_LANE_034_BIST_GEN_CDN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_INSERT_LENGTH_O_2_0_MASK (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_INSERT_LENGTH_O_2_0_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_INSERT_LENGTH_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM0_O_9_8_MASK (0x00000003u)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM0_O_9_8_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_034_BIST_CHK_PREAM0_O_9_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_034_RESETVAL   (0x00000000u)

/* lane_038 */

#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_31_24_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_31_24_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_31_24_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_23_16_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_23_16_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_23_16_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_15_8_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_15_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_038_BIST_CHK_UDP_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_038_RESETVAL   (0x00000000u)

/* lane_03c */

#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_23_16_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_23_16_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_23_16_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_15_8_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_15_8_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_INSERT_WORD_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_UDP_O_39_32_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_UDP_O_39_32_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_03C_BIST_CHK_UDP_O_39_32_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_03C_RESETVAL   (0x00000000u)

/* lane_040 */

#define CSL_WIZ8B8SB_LANE_040_BIST_GEN_EN_LOW_O_15_8_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_040_BIST_GEN_EN_LOW_O_15_8_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_040_BIST_GEN_EN_LOW_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_040_BIST_GEN_EN_LOW_O_7_0_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_040_BIST_GEN_EN_LOW_O_7_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_040_BIST_GEN_EN_LOW_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_040_BIST_CHK_INSERT_WORD_O_39_32_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_040_BIST_CHK_INSERT_WORD_O_39_32_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_040_BIST_CHK_INSERT_WORD_O_39_32_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_040_BIST_CHK_INSERT_WORD_O_31_24_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_040_BIST_CHK_INSERT_WORD_O_31_24_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_040_BIST_CHK_INSERT_WORD_O_31_24_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_040_RESETVAL   (0x00000000u)

/* lane_044 */

#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_INSERT_DELAY_O_11_8_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_INSERT_DELAY_O_11_8_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_INSERT_DELAY_O_11_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_INSERT_DELAY_O_7_0_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_INSERT_DELAY_O_7_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_INSERT_DELAY_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_EN_HIGH_O_15_8_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_EN_HIGH_O_15_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_EN_HIGH_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_EN_HIGH_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_EN_HIGH_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_044_BIST_GEN_EN_HIGH_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_044_RESETVAL   (0x00000000u)

/* lane_048 */

#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_READ_OVR_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_READ_OVR_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_READ_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_GO_OVR_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_GO_OVR_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_GO_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_LATCH_OVR_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_LATCH_OVR_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_LATCH_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_DATA_OVR_O_11_7_MASK (0x1F000000u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_DATA_OVR_O_11_7_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_DATA_OVR_O_11_7_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_DATA_OVR_O_6_0_MASK (0x00FE0000u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_DATA_OVR_O_6_0_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_PMA_DATA_OVR_O_6_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_OUT_OVR_EN_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_OUT_OVR_EN_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_048_GCFSM_LANE_OUT_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_BIST_CHK_ERROR_15_8_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_048_BIST_CHK_ERROR_15_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_048_BIST_CHK_ERROR_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_BIST_CHK_ERROR_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_048_BIST_CHK_ERROR_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_048_BIST_CHK_ERROR_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_048_RESETVAL   (0x00000000u)

/* lane_04c */

#define CSL_WIZ8B8SB_LANE_04C_AHB_JTAG_OVR_O_6_0_MASK (0xFE000000u)
#define CSL_WIZ8B8SB_LANE_04C_AHB_JTAG_OVR_O_6_0_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_LANE_04C_AHB_JTAG_OVR_O_6_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_04C_AHB_JTAG_OVR_ENA_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_LANE_04C_AHB_JTAG_OVR_ENA_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_04C_AHB_JTAG_OVR_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_04C_PMA_LN_DFE_BIAS_O_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_LANE_04C_PMA_LN_DFE_BIAS_O_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_04C_PMA_LN_DFE_BIAS_O_3_0_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_LANE_04C_RX_ATT_BOOST_NORM_O_1_0_MASK (0x000C0000u)
#define CSL_WIZ8B8SB_LANE_04C_RX_ATT_BOOST_NORM_O_1_0_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_LANE_04C_RX_ATT_BOOST_NORM_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_04C_RX_ATT_BOOST_CAL_O_1_0_MASK (0x00030000u)
#define CSL_WIZ8B8SB_LANE_04C_RX_ATT_BOOST_CAL_O_1_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_04C_RX_ATT_BOOST_CAL_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_04C_GCFSM_LANE_PMA_CAL_OVR_O_15_8_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_04C_GCFSM_LANE_PMA_CAL_OVR_O_15_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_04C_GCFSM_LANE_PMA_CAL_OVR_O_15_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_04C_GCFSM_LANE_PMA_CAL_OVR_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_04C_GCFSM_LANE_PMA_CAL_OVR_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_04C_GCFSM_LANE_PMA_CAL_OVR_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_04C_RESETVAL   (0x00800000u)

/* lane_050 */

#define CSL_WIZ8B8SB_LANE_050_DEC_EN_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_050_DEC_EN_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_050_DEC_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_ENC_EN_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_LANE_050_ENC_EN_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_LANE_050_ENC_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_MODE_8B_O_1_0_MASK (0x30000000u)
#define CSL_WIZ8B8SB_LANE_050_MODE_8B_O_1_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_050_MODE_8B_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXBIT_REPEAT_O_MASK (0x0C000000u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXBIT_REPEAT_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXBIT_REPEAT_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_UNDEFINED_10_MASK (0x03000000u)
#define CSL_WIZ8B8SB_LANE_050_UNDEFINED_10_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_050_UNDEFINED_10_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXMAC_CLK_DIV_O_MASK (0x00C00000u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXMAC_CLK_DIV_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXMAC_CLK_DIV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXMAC_CLK_SRC_O_MASK (0x00300000u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXMAC_CLK_SRC_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_TXMAC_CLK_SRC_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_AHB_LN_RXMAC_CLK_DIV_O_MASK (0x000C0000u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_RXMAC_CLK_DIV_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_RXMAC_CLK_DIV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_UNDEFINED_09_MASK (0x00030000u)
#define CSL_WIZ8B8SB_LANE_050_UNDEFINED_09_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_050_UNDEFINED_09_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_LBENC_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_LANE_050_LBENC_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_LANE_050_LBENC_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_AHB_PMA_RATE2_SD_THSEL_2_0_O_MASK (0x00003800u)
#define CSL_WIZ8B8SB_LANE_050_AHB_PMA_RATE2_SD_THSEL_2_0_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_050_AHB_PMA_RATE2_SD_THSEL_2_0_O_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_050_AHB_PMA_RATE1_SD_THSEL_2_0_O_MASK (0x00000700u)
#define CSL_WIZ8B8SB_LANE_050_AHB_PMA_RATE1_SD_THSEL_2_0_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_050_AHB_PMA_RATE1_SD_THSEL_2_0_O_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_050_AHB_LN_RXBIT_STRIP_O_MASK (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_RXBIT_STRIP_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_050_AHB_LN_RXBIT_STRIP_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_AHB_BEACON_ENA_OVR_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANE_050_AHB_BEACON_ENA_OVR_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_050_AHB_BEACON_ENA_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_AHB_BEACON_ENA_OVR_ENA_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_050_AHB_BEACON_ENA_OVR_ENA_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_050_AHB_BEACON_ENA_OVR_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_050_RESETVAL   (0x00001B00u)

/* lane_054 */

#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_14_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_14_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_14_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_13_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_13_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_13_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_12_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_12_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_12_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_11_MASK (0x00000007u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_11_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_054_UNDEFINED_11_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_054_RESETVAL   (0x00000000u)

/* lane_058 */

#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_17_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_17_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_17_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_DFE_TAP1_OVR_VAL_O_6_0_MASK (0x7F000000u)
#define CSL_WIZ8B8SB_LANE_058_DFE_TAP1_OVR_VAL_O_6_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_058_DFE_TAP1_OVR_VAL_O_6_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_MASK (0x00F80000u)
#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_DFE_CMP_CAL_EN_OVR_O_2_MASK (0x00040000u)
#define CSL_WIZ8B8SB_LANE_058_DFE_CMP_CAL_EN_OVR_O_2_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_LANE_058_DFE_CMP_CAL_EN_OVR_O_2_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_EN_OVR_O_1_MASK (0x00020000u)
#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_EN_OVR_O_1_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_EN_OVR_O_1_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_MASK (0x00010000u)
#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_058_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_16_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_16_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_16_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_15_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_15_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_058_UNDEFINED_15_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_058_RESETVAL   (0x00000000u)

/* lane_05c */

#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP_OVR_EN_O_7_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP_OVR_EN_O_7_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP_OVR_EN_O_7_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_MASK (0x40000000u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP5_OVR_VAL_O_5_0_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP5_OVR_VAL_O_5_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP5_OVR_VAL_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_20_MASK (0x00C00000u)
#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_20_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_20_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP4_OVR_VAL_O_5_0_MASK (0x003F0000u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP4_OVR_VAL_O_5_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP4_OVR_VAL_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_19_MASK (0x0000C000u)
#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_19_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_19_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP3_OVR_VAL_O_5_0_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP3_OVR_VAL_O_5_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP3_OVR_VAL_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_18_MASK (0x000000C0u)
#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_18_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_LANE_05C_UNDEFINED_18_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP2_OVR_VAL_O_5_0_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP2_OVR_VAL_O_5_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_05C_DFE_TAP2_OVR_VAL_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_05C_RESETVAL   (0x00000000u)

/* lane_060 */

#define CSL_WIZ8B8SB_LANE_060_PMA_CMU_SEL_O_0_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_060_PMA_CMU_SEL_O_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_060_PMA_CMU_SEL_O_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_060_RESETVAL   (0x00000000u)

/* lane_078 */

#define CSL_WIZ8B8SB_LANE_078_CMP_OFFSET_AVG_EN_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_078_CMP_OFFSET_AVG_EN_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_078_CMP_OFFSET_AVG_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_078_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_MASK (0x7F000000u)
#define CSL_WIZ8B8SB_LANE_078_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_078_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_LANE_078_AHB_TX_CDAC_OVR_MASK (0x001E0000u)
#define CSL_WIZ8B8SB_LANE_078_AHB_TX_CDAC_OVR_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_LANE_078_AHB_TX_CDAC_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_078_AHB_TX_TERM_EN_CAL_OVR_MASK (0x00010000u)
#define CSL_WIZ8B8SB_LANE_078_AHB_TX_TERM_EN_CAL_OVR_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_078_AHB_TX_TERM_EN_CAL_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_078_PMA_LN_TXEQ_POLARITY_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_078_PMA_LN_TXEQ_POLARITY_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_078_PMA_LN_TXEQ_POLARITY_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_LANE_078_PMA_LN_TX_SR_FASTCAP_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_078_PMA_LN_TX_SR_FASTCAP_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_078_PMA_LN_TX_SR_FASTCAP_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_078_RESETVAL   (0x8F005000u)

/* lane_07c */

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_OVR_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_OVR_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_OVR_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_OVR_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_MARGIN_ADD_MASK (0x00200000u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_MARGIN_ADD_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_MARGIN_ADD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CX_OVR_ENA_MASK (0x00100000u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CX_OVR_ENA_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CX_OVR_ENA_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_RESETVAL (0x00000009u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_WAIT_NEXT_SAMPLE_MASK (0x0000E000u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_WAIT_NEXT_SAMPLE_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_WAIT_NEXT_SAMPLE_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_WAIT_NEXT_CMP_MASK (0x00001E00u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_WAIT_NEXT_CMP_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_TC_WAIT_NEXT_CMP_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_MARGIN_ADD_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_MARGIN_ADD_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_MARGIN_ADD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_MARGIN_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_MARGIN_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXN_MARGIN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_MARGIN_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_MARGIN_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_07C_AHB_TX_CXP_MARGIN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_07C_RESETVAL   (0x00092A00u)

/* lane_080 */

#define CSL_WIZ8B8SB_LANE_080_UNDEFINED_22_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_080_UNDEFINED_22_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_080_UNDEFINED_22_RESETVAL (0x00000050u)

#define CSL_WIZ8B8SB_LANE_080_CDR_CTRL_TIMING_WINDOW_LEN_7_0_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_LANE_080_CDR_CTRL_TIMING_WINDOW_LEN_7_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_080_CDR_CTRL_TIMING_WINDOW_LEN_7_0_RESETVAL (0x00000080u)

#define CSL_WIZ8B8SB_LANE_080_UNDEFINED_21_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_LANE_080_UNDEFINED_21_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_080_UNDEFINED_21_RESETVAL (0x00000050u)

#define CSL_WIZ8B8SB_LANE_080_GCFSM_LANE_TIMING_WINDOW_LEN_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_LANE_080_GCFSM_LANE_TIMING_WINDOW_LEN_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_080_GCFSM_LANE_TIMING_WINDOW_LEN_7_0_RESETVAL (0x00000080u)

#define CSL_WIZ8B8SB_LANE_080_RESETVAL   (0x50805080u)

/* lane_084 */

#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE2_BOOST_START_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE2_BOOST_START_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE2_BOOST_START_O_3_0_RESETVAL (0x00000006u)

#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE2_ATT_START_O_3_0_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE2_ATT_START_O_3_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE2_ATT_START_O_3_0_RESETVAL (0x0000000Du)

#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE1_BOOST_START_O_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE1_BOOST_START_O_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE1_BOOST_START_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE1_ATT_START_O_3_0_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE1_ATT_START_O_3_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_084_RXEQ_RATE1_ATT_START_O_3_0_RESETVAL (0x00000009u)

#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TXDRV_BLEED_ENA_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TXDRV_BLEED_ENA_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TXDRV_BLEED_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TX_SR_DAC_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TX_SR_DAC_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TX_SR_DAC_O_3_0_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TX_VREG_LEV_O_2_0_MASK (0x000000E0u)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TX_VREG_LEV_O_2_0_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_TX_VREG_LEV_O_2_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_084_PMA_LN_HSCLK_SEL_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_HSCLK_SEL_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_084_PMA_LN_HSCLK_SEL_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_084_CDR_CTRL_CAL_LOAD_OVR_MASK (0x00000008u)
#define CSL_WIZ8B8SB_LANE_084_CDR_CTRL_CAL_LOAD_OVR_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_084_CDR_CTRL_CAL_LOAD_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_084_CDR_CTRL_TW_METHOD_EN_MASK (0x00000004u)
#define CSL_WIZ8B8SB_LANE_084_CDR_CTRL_TW_METHOD_EN_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_084_CDR_CTRL_TW_METHOD_EN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_084_GCFSM_LANE_PMA_LOAD_OVR_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANE_084_GCFSM_LANE_PMA_LOAD_OVR_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_084_GCFSM_LANE_PMA_LOAD_OVR_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_084_GCFSM_LANE_TW_METHOD_EN_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_084_GCFSM_LANE_TW_METHOD_EN_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_084_GCFSM_LANE_TW_METHOD_EN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_084_RESETVAL   (0x6D491F90u)

/* lane_088 */

#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP4_START_O_5_0_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP4_START_O_5_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP4_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP3_START_O_5_0_MASK (0x003F0000u)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP3_START_O_5_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP3_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP2_START_O_5_0_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP2_START_O_5_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP2_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP1_START_O_6_0_MASK (0x0000007Fu)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP1_START_O_6_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_088_RXEQ_RATE2_TAP1_START_O_6_0_RESETVAL (0x00000040u)

#define CSL_WIZ8B8SB_LANE_088_RESETVAL   (0x20202040u)

/* lane_08c */

#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_TAP2_START_O_5_0_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_TAP2_START_O_5_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_TAP2_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_TAP1_START_O_6_0_MASK (0x007F0000u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_TAP1_START_O_6_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_TAP1_START_O_6_0_RESETVAL (0x00000040u)

#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_BOOST_START_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_BOOST_START_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_BOOST_START_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_ATT_START_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_ATT_START_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE3_ATT_START_O_3_0_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE2_TAP5_START_O_5_0_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE2_TAP5_START_O_5_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_08C_RXEQ_RATE2_TAP5_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_08C_RESETVAL   (0x20404820u)

/* lane_090 */

#define CSL_WIZ8B8SB_LANE_090_TXCTRL_RATE1_LOWSWG_TX_SR_FASTCAP_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_090_TXCTRL_RATE1_LOWSWG_TX_SR_FASTCAP_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_090_TXCTRL_RATE1_LOWSWG_TX_SR_FASTCAP_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_090_TXCTRL_RATE1_FULLSWG_TX_SR_FASTCAP_O_3_0_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_090_TXCTRL_RATE1_FULLSWG_TX_SR_FASTCAP_O_3_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_090_TXCTRL_RATE1_FULLSWG_TX_SR_FASTCAP_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP5_START_O_5_0_MASK (0x003F0000u)
#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP5_START_O_5_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP5_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP4_START_O_5_0_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP4_START_O_5_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP4_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP3_START_O_5_0_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP3_START_O_5_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_090_RXEQ_RATE3_TAP3_START_O_5_0_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_LANE_090_RESETVAL   (0x00202020u)

/* lane_094 */

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SR_DAC_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SR_DAC_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SR_DAC_O_3_0_RESETVAL (0x00000006u)

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_6DB_TX_SR_DAC_O_3_0_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_6DB_TX_SR_DAC_O_3_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_6DB_TX_SR_DAC_O_3_0_RESETVAL (0x00000006u)

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_LOWSWG_TX_SR_DAC_O_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_LOWSWG_TX_SR_DAC_O_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_LOWSWG_TX_SR_DAC_O_3_0_RESETVAL (0x00000006u)

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE1_LOWSWG_TX_SR_DAC_O_3_0_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE1_LOWSWG_TX_SR_DAC_O_3_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE1_LOWSWG_TX_SR_DAC_O_3_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE1_FULLSWG_TX_SR_DAC_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE1_FULLSWG_TX_SR_DAC_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE1_FULLSWG_TX_SR_DAC_O_3_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SR_FASTCAP_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SR_FASTCAP_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SR_FASTCAP_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_LOWSWG_TX_SR_FASTCAP_O_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_LOWSWG_TX_SR_FASTCAP_O_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_LOWSWG_TX_SR_FASTCAP_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_6DB_TX_SR_FASTCAP_O_3_0_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_6DB_TX_SR_FASTCAP_O_3_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_094_TXCTRL_RATE2_FULLSWG_6DB_TX_SR_FASTCAP_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_094_RESETVAL   (0x66633000u)

/* lane_098 */

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RESETVAL (0x00000007u)

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RESETVAL (0x00000009u)

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_FULLSWG_3P5DB_TXEQ_POLARITY_O_3_0_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_FULLSWG_3P5DB_TXEQ_POLARITY_O_3_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_FULLSWG_3P5DB_TXEQ_POLARITY_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_FULLSWG_6DB_TXEQ_POLARITY_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_FULLSWG_6DB_TXEQ_POLARITY_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_FULLSWG_6DB_TXEQ_POLARITY_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_LOWSWG_TXEQ_POLARITY_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_LOWSWG_TXEQ_POLARITY_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE2_LOWSWG_TXEQ_POLARITY_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE1_LOWSWG_TXEQ_POLARITY_O_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE1_LOWSWG_TXEQ_POLARITY_O_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE1_LOWSWG_TXEQ_POLARITY_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE1_FULLSWG_TXEQ_POLARITY_O_3_0_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE1_FULLSWG_TXEQ_POLARITY_O_3_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_098_TXCTRL_RATE1_FULLSWG_TXEQ_POLARITY_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_LANE_098_RESETVAL   (0x79F44444u)

/* lane_09c */

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE2_LOWSWG_C1_IN_O_4_0_MASK (0xF8000000u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE2_LOWSWG_C1_IN_O_4_0_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE2_LOWSWG_C1_IN_O_4_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE2_LOWSWG_TX_SLEW_SLD3F_O_2_0_MASK (0x07000000u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE2_LOWSWG_TX_SLEW_SLD3F_O_2_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE2_LOWSWG_TX_SLEW_SLD3F_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_LOWSWG_C1_IN_O_4_0_MASK (0x00F80000u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_LOWSWG_C1_IN_O_4_0_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_LOWSWG_C1_IN_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_LOWSWG_TX_SLEW_SLD3F_O_2_0_MASK (0x00070000u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_LOWSWG_TX_SLEW_SLD3F_O_2_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_LOWSWG_TX_SLEW_SLD3F_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_FULLSWG_C1_IN_O_4_0_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_FULLSWG_C1_IN_O_4_0_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_FULLSWG_C1_IN_O_4_0_RESETVAL (0x00000006u)

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_FULLSWG_TX_SLEW_SLD3F_O_2_0_MASK (0x00000700u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_FULLSWG_TX_SLEW_SLD3F_O_2_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_RATE1_FULLSWG_TX_SLEW_SLD3F_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_09C_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_LANE_09C_RESETVAL   (0x10003002u)

/* lane_0a0 */

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_C1_IN_OVR_EN_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_C1_IN_OVR_EN_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_C1_IN_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_PREEM_1LSB_MODE_OVR_EN_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_PREEM_1LSB_MODE_OVR_EN_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_PREEM_1LSB_MODE_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_TX_SLEW_SLD_O_1_0_MASK (0x30000000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_TX_SLEW_SLD_O_1_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_TX_SLEW_SLD_O_1_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SLEW_SLD_OVR_EN_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SLEW_SLD_OVR_EN_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SLEW_SLD_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SLEW_SLD3F_OVR_EN_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SLEW_SLD3F_OVR_EN_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SLEW_SLD3F_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_LOWSWG_TX_SLEW_SLD_O_1_0_MASK (0x03000000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_LOWSWG_TX_SLEW_SLD_O_1_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_LOWSWG_TX_SLEW_SLD_O_1_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_ATT_IN_OVR_EN_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_ATT_IN_OVR_EN_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_ATT_IN_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TXEQ_POLARITY_OVR_EN_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TXEQ_POLARITY_OVR_EN_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TXEQ_POLARITY_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE1_LOWSWG_TX_SLEW_SLD_O_1_0_MASK (0x00300000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE1_LOWSWG_TX_SLEW_SLD_O_1_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE1_LOWSWG_TX_SLEW_SLD_O_1_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SR_DAC_OVR_EN_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SR_DAC_OVR_EN_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SR_DAC_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SR_FASTCAP_OVR_EN_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SR_FASTCAP_OVR_EN_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_TX_SR_FASTCAP_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE1_FULLSWG_TX_SLEW_SLD_O_1_0_MASK (0x00030000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE1_FULLSWG_TX_SLEW_SLD_O_1_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE1_FULLSWG_TX_SLEW_SLD_O_1_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_O_4_0_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_O_4_0_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_O_4_0_RESETVAL (0x00000006u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SLEW_SLD3F_O_2_0_MASK (0x00000700u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SLEW_SLD3F_O_2_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SLEW_SLD3F_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_C1_IN_O_4_0_MASK (0x000000F8u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_C1_IN_O_4_0_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_C1_IN_O_4_0_RESETVAL (0x00000009u)

#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_TX_SLEW_SLD3F_O_2_0_MASK (0x00000007u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_TX_SLEW_SLD3F_O_2_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_0A0_TXCTRL_RATE2_FULLSWG_6DB_TX_SLEW_SLD3F_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A0_RESETVAL   (0x33223048u)

/* lane_0a4 */

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_CM_IN_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_CM_IN_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_CM_IN_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_C2_IN_2_0_MASK (0x0E000000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_C2_IN_2_0_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_C2_IN_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_PREEM_1LSB_MODE_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_PREEM_1LSB_MODE_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_LOWSWG_PREEM_1LSB_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_CM_IN_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_CM_IN_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_CM_IN_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_C2_IN_2_0_MASK (0x000E0000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_C2_IN_2_0_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_C2_IN_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_PREEM_1LSB_MODE_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_PREEM_1LSB_MODE_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_LOWSWG_PREEM_1LSB_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_CM_IN_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_CM_IN_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_CM_IN_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_C2_IN_2_0_MASK (0x00000E00u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_C2_IN_2_0_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_C2_IN_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_PREEM_1LSB_MODE_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_PREEM_1LSB_MODE_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE1_FULLSWG_PREEM_1LSB_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_CM_IN_OVR_EN_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_CM_IN_OVR_EN_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_CM_IN_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_C2_IN_OVR_EN_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_C2_IN_OVR_EN_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_C2_IN_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SLEW_SLD_O_1_0_MASK (0x00000003u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SLEW_SLD_O_1_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_0A4_TXCTRL_RATE2_FULLSWG_3P5DB_TX_SLEW_SLD_O_1_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_0A4_RESETVAL   (0x00000003u)

/* lane_0a8 */

#define CSL_WIZ8B8SB_LANE_0A8_GCFSM_DFE_OFFSET_CAL_1ST_CYC_START_LEN_O_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_0A8_GCFSM_DFE_OFFSET_CAL_1ST_CYC_START_LEN_O_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_0A8_GCFSM_DFE_OFFSET_CAL_1ST_CYC_START_LEN_O_7_0_RESETVAL (0x00000050u)

#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_MASTER_OVR_EN_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_MASTER_OVR_EN_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_MASTER_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_CM_IN_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_CM_IN_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_CM_IN_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_2_0_MASK (0x00000E00u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_2_0_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_PREEM_1LSB_MODE_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_PREEM_1LSB_MODE_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_3P5DB_PREEM_1LSB_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_CM_IN_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_CM_IN_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_CM_IN_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_C2_IN_2_0_MASK (0x0000000Eu)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_C2_IN_2_0_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_C2_IN_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_PREEM_1LSB_MODE_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_PREEM_1LSB_MODE_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_0A8_TXCTRL_RATE2_FULLSWG_6DB_PREEM_1LSB_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0A8_RESETVAL   (0x50000000u)

/* lane_0ac */

#define CSL_WIZ8B8SB_LANE_0AC_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_0AC_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_0AC_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0AC_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_0AC_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_0AC_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0AC_LN_P2S_RBUF_REALIGN_DIFF_O_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_LANE_0AC_LN_P2S_RBUF_REALIGN_DIFF_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_0AC_LN_P2S_RBUF_REALIGN_DIFF_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0AC_LN_TO_CLK_TXB_WAIT_O_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_LANE_0AC_LN_TO_CLK_TXB_WAIT_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_LANE_0AC_LN_TO_CLK_TXB_WAIT_O_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_LANE_0AC_LN_COMMON_SYNC_TXCLK_EN_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_LANE_0AC_LN_COMMON_SYNC_TXCLK_EN_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_LANE_0AC_LN_COMMON_SYNC_TXCLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0AC_LN_CLK_TXB_DIV24OR1_O_MASK (0x00000300u)
#define CSL_WIZ8B8SB_LANE_0AC_LN_CLK_TXB_DIV24OR1_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0AC_LN_CLK_TXB_DIV24OR1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0AC_AHB_LN_IN_OVR_CHG_FLAG_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANE_0AC_AHB_LN_IN_OVR_CHG_FLAG_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANE_0AC_AHB_LN_IN_OVR_CHG_FLAG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0AC_BIST_CHK_SYNC_ON_ZEROS_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANE_0AC_BIST_CHK_SYNC_ON_ZEROS_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_0AC_BIST_CHK_SYNC_ON_ZEROS_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0AC_RESETVAL   (0x00004000u)

/* lane_0b0 */

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_I_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_I_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_I_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_I_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_I_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_I_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_I_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_I_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_I_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_I_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_I_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_I_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_I_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_I_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_I_RESETVAL (0x0000000Bu)

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_I_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_I_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_I_RESETVAL (0x0000000Du)

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_I_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_I_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_I_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_0B0_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B0_RESETVAL   (0x1238BDF0u)

/* lane_0b4 */

#define CSL_WIZ8B8SB_LANE_0B4_AHB_BEACON_DELAYED_COUNT_NUMBER_7_0_O_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_LANE_0B4_AHB_BEACON_DELAYED_COUNT_NUMBER_7_0_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANE_0B4_AHB_BEACON_DELAYED_COUNT_NUMBER_7_0_O_RESETVAL (0x000000D0u)

#define CSL_WIZ8B8SB_LANE_0B4_EN_PROG_TXDETECTRX_PULSE_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_LANE_0B4_EN_PROG_TXDETECTRX_PULSE_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_LANE_0B4_EN_PROG_TXDETECTRX_PULSE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B4_PROG_TXDETECTRX_PULSE_WIDTH_O_0_5_MASK (0x003F0000u)
#define CSL_WIZ8B8SB_LANE_0B4_PROG_TXDETECTRX_PULSE_WIDTH_O_0_5_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_0B4_PROG_TXDETECTRX_PULSE_WIDTH_O_0_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B4_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_MASK (0x00001F00u)
#define CSL_WIZ8B8SB_LANE_0B4_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0B4_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_RESETVAL (0x0000000Au)

#define CSL_WIZ8B8SB_LANE_0B4_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_I_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_0B4_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_I_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_0B4_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_I_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B4_RESETVAL   (0xD0000A00u)

/* lane_0b8 */

#define CSL_WIZ8B8SB_LANE_0B8_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B8_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B8_AHB_EBUF_ALIGN_WORD_DETECT_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_EBUF_ALIGN_WORD_DETECT_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_EBUF_ALIGN_WORD_DETECT_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_DIR_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_DIR_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_DIR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_EN_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_EN_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_VAL_O_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_VAL_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_LANE_0B8_BOOST_ADJ_VAL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANE_0B8_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANE_0B8_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_RESETVAL (0x00000007u)

#define CSL_WIZ8B8SB_LANE_0B8_RESETVAL   (0x00000407u)

/* comlane_000 */

#define CSL_WIZ8B8SB_COMLANE_000_OOB_DET_BLEN_MIN_O_6_0_MASK (0xFE000000u)
#define CSL_WIZ8B8SB_COMLANE_000_OOB_DET_BLEN_MIN_O_6_0_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_000_OOB_DET_BLEN_MIN_O_6_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_000_QD_CLK_SRC_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_000_QD_CLK_SRC_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_000_QD_CLK_SRC_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_UNDEFINED_01_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_000_UNDEFINED_01_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_000_UNDEFINED_01_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_RXEQ_RATE_OW_O_2_0_MASK (0x00700000u)
#define CSL_WIZ8B8SB_COMLANE_000_RXEQ_RATE_OW_O_2_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_000_RXEQ_RATE_OW_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_OOB_DIV_EN_O_1_0_MASK (0x000C0000u)
#define CSL_WIZ8B8SB_COMLANE_000_OOB_DIV_EN_O_1_0_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_000_OOB_DIV_EN_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_UNDEFINED_00_MASK (0x00030000u)
#define CSL_WIZ8B8SB_COMLANE_000_UNDEFINED_00_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_000_UNDEFINED_00_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_RXEQ_CDR_LOCK_WAIT_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_COMLANE_000_RXEQ_CDR_LOCK_WAIT_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_000_RXEQ_CDR_LOCK_WAIT_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_COMLANE_000_PIPE_EN_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_000_PIPE_EN_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_000_PIPE_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_SAPIS_EN_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_COMLANE_000_SAPIS_EN_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_000_SAPIS_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_000_RLD_EN_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_COMLANE_000_RLD_EN_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_000_RLD_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_L3_MASTER_CDN_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_000_L3_MASTER_CDN_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_000_L3_MASTER_CDN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_L2_MASTER_CDN_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_000_L2_MASTER_CDN_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_000_L2_MASTER_CDN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_L1_MASTER_CDN_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_000_L1_MASTER_CDN_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_000_L1_MASTER_CDN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_L0_MASTER_CDN_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_000_L0_MASTER_CDN_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_000_L0_MASTER_CDN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_LC_MASTER_CDN_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_000_LC_MASTER_CDN_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_000_LC_MASTER_CDN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_000_RESETVAL (0x04000440u)

/* comlane_004 */

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MAX_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MAX_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MAX_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MIN_O_6_3_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MIN_O_6_3_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MIN_O_6_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MIN_O_2_0_MASK (0x00E00000u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MIN_O_2_0_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMWAKE_MIN_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MAX_O_6_2_MASK (0x001F0000u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MAX_O_6_2_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MAX_O_6_2_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MAX_O_1_0_MASK (0x0000C000u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MAX_O_1_0_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MAX_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MIN_O_6_1_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MIN_O_6_1_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MIN_O_6_1_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MIN_O_0_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MIN_O_0_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_COMINIT_MIN_O_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_BLEN_MAX_O_6_0_MASK (0x0000007Fu)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_BLEN_MAX_O_6_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_004_OOB_DET_BLEN_MAX_O_6_0_RESETVAL (0x0000001Eu)

#define CSL_WIZ8B8SB_COMLANE_004_RESETVAL (0x0000001Eu)

/* comlane_008 */

#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_START_LEN_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_START_LEN_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_START_LEN_O_3_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_CYCLE_LEN_O_7_4_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_CYCLE_LEN_O_7_4_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_CYCLE_LEN_O_7_4_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_CYCLE_LEN_O_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_CYCLE_LEN_O_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_CYCLE_LEN_O_3_0_RESETVAL (0x0000000Eu)

#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_LANE_O_9_6_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_LANE_O_9_6_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_LANE_O_9_6_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_LANE_O_5_0_MASK (0x0000FC00u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_LANE_O_5_0_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_LANE_O_5_0_RESETVAL (0x00000021u)

#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_CDR_O_6_5_MASK (0x00000300u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_CDR_O_6_5_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_CDR_O_6_5_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_CDR_O_4_0_MASK (0x000000F8u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_CDR_O_4_0_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_008_CDR_CTRL_DLY_CDR_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_008_OOB_DET_COMWAKE_MAX_O_6_4_MASK (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_008_OOB_DET_COMWAKE_MAX_O_6_4_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_008_OOB_DET_COMWAKE_MAX_O_6_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_008_RESETVAL (0x32E28500u)

/* comlane_00c */

#define CSL_WIZ8B8SB_COMLANE_00C_SYM_LOCK_NUM_O_2_0_MASK (0xE0000000u)
#define CSL_WIZ8B8SB_COMLANE_00C_SYM_LOCK_NUM_O_2_0_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_00C_SYM_LOCK_NUM_O_2_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_00C_SYM_ALIGN_WORD_O_9_5_MASK (0x1F000000u)
#define CSL_WIZ8B8SB_COMLANE_00C_SYM_ALIGN_WORD_O_9_5_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_00C_SYM_ALIGN_WORD_O_9_5_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_00C_SYM_ALIGN_WORD_O_4_0_MASK (0x00F80000u)
#define CSL_WIZ8B8SB_COMLANE_00C_SYM_ALIGN_WORD_O_4_0_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_00C_SYM_ALIGN_WORD_O_4_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_00C_RLD_MAXLEN_O_6_4_MASK (0x00070000u)
#define CSL_WIZ8B8SB_COMLANE_00C_RLD_MAXLEN_O_6_4_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_00C_RLD_MAXLEN_O_6_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_00C_RLD_MAXLEN_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_COMLANE_00C_RLD_MAXLEN_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_00C_RLD_MAXLEN_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_00C_CDRCTRL_DIV_EN_O_1_0_MASK (0x00000C00u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDRCTRL_DIV_EN_O_1_0_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_00C_CDRCTRL_DIV_EN_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MIN_BOUNCE_O_2_1_MASK (0x00000300u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MIN_BOUNCE_O_2_1_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MIN_BOUNCE_O_2_1_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MIN_BOUNCE_O_0_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MIN_BOUNCE_O_0_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MIN_BOUNCE_O_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MAX_DIFF_O_4_0_MASK (0x0000007Cu)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MAX_DIFF_O_4_0_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_MAX_DIFF_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_INT_FIL_O_1_0_MASK (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_INT_FIL_O_1_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_00C_CDR_CTRL_INT_FIL_O_1_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_00C_RESETVAL (0x74180182u)

/* comlane_010 */

#define CSL_WIZ8B8SB_COMLANE_010_FAST_SIM_O_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_010_FAST_SIM_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_010_FAST_SIM_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_010_GCFSM_DIV_EN_O_1_0_MASK (0x00000600u)
#define CSL_WIZ8B8SB_COMLANE_010_GCFSM_DIV_EN_O_1_0_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_010_GCFSM_DIV_EN_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_010_P2S_RBUF_AUTOFIX_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_010_P2S_RBUF_AUTOFIX_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_010_P2S_RBUF_AUTOFIX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_010_P2S_RBUF_PTR_DIFF_O_2_0_MASK (0x000000E0u)
#define CSL_WIZ8B8SB_COMLANE_010_P2S_RBUF_PTR_DIFF_O_2_0_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_010_P2S_RBUF_PTR_DIFF_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_010_SYM_UNLOCK_NUM_O_3_0_MASK (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_010_SYM_UNLOCK_NUM_O_3_0_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_010_SYM_UNLOCK_NUM_O_3_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_010_SYM_LOCK_NUM_O_3_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_010_SYM_LOCK_NUM_O_3_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_010_SYM_LOCK_NUM_O_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_010_RESETVAL (0x00000006u)

/* comlane_014 */

#define CSL_WIZ8B8SB_COMLANE_014_BIST_GEN_INV_PRBS_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_014_BIST_GEN_INV_PRBS_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_014_BIST_GEN_INV_PRBS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_014_BIST_CHK_INV_PRBS_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_014_BIST_CHK_INV_PRBS_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_014_BIST_CHK_INV_PRBS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_014_RESETVAL (0x00000000u)

/* comlane_018 */

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_N_O_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_N_O_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_N_O_7_0_RESETVAL (0x000000BCu)

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_EN_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_EN_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_O_9_3_MASK (0x007F0000u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_O_9_3_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_O_9_3_RESETVAL (0x00000068u)

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_FIFO_EMPTY_O_4_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_FIFO_EMPTY_O_4_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_FIFO_EMPTY_O_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_MODE_O_1_0_MASK (0x00006000u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_MODE_O_1_0_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_MODE_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB0_O_9_5_MASK (0x00001F00u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB0_O_9_5_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB0_O_9_5_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_O_2_0_MASK (0x000000E0u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_O_2_0_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB1_O_2_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB0_O_4_0_MASK (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB0_O_4_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_018_EBUF_SYMB0_O_4_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_018_RESETVAL (0xBC681463u)

/* comlane_01c */

#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_EMPTY_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_EMPTY_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_EMPTY_O_3_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_FULL_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_FULL_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_FULL_O_3_0_RESETVAL (0x0000000Eu)

#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_FULL_O_4_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_FULL_O_4_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_FULL_O_4_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_MID_O_4_0_MASK (0x0000007Cu)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_MID_O_4_0_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_FIFO_MID_O_4_0_RESETVAL (0x00000010u)

#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_SYMB1_N_O_9_8_MASK (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_SYMB1_N_O_9_8_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_01C_EBUF_SYMB1_N_O_9_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_01C_RESETVAL (0x00002EC0u)

/* comlane_030 */

#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_23_16_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_23_16_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_23_16_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_15_8_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_15_8_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_15_8_RESETVAL (0x0000002Eu)

#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_030_GCFSM_CYCLE_LEN_O_7_0_RESETVAL (0x0000002Eu)

#define CSL_WIZ8B8SB_COMLANE_030_UNDEFINED_02_MASK (0x0000007Fu)
#define CSL_WIZ8B8SB_COMLANE_030_UNDEFINED_02_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_030_UNDEFINED_02_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_030_RESETVAL (0x142E2E00u)

/* comlane_034 */

#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_55_48_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_55_48_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_55_48_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_47_40_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_47_40_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_47_40_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_39_32_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_39_32_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_39_32_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_31_24_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_31_24_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_034_GCFSM_CYCLE_LEN_O_31_24_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_034_RESETVAL (0x14141414u)

/* comlane_038 */

#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_87_80_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_87_80_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_87_80_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_79_72_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_79_72_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_79_72_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_71_64_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_71_64_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_71_64_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_63_56_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_63_56_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_038_GCFSM_CYCLE_LEN_O_63_56_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_038_RESETVAL (0x00000014u)

/* comlane_03c */

#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_119_112_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_119_112_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_119_112_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_111_104_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_111_104_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_111_104_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_103_96_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_103_96_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_103_96_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_95_88_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_95_88_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_03C_GCFSM_CYCLE_LEN_O_95_88_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_03C_RESETVAL (0x00000000u)

/* comlane_040 */

#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_05_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_05_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_05_RESETVAL (0x000000E4u)

#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_04_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_04_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_04_RESETVAL (0x0000004Cu)

#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_03_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_03_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_040_UNDEFINED_03_RESETVAL (0x00000095u)

#define CSL_WIZ8B8SB_COMLANE_040_GCFSM_CYCLE_LEN_O_127_120_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_040_GCFSM_CYCLE_LEN_O_127_120_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_040_GCFSM_CYCLE_LEN_O_127_120_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_040_RESETVAL (0xE44C9500u)

/* comlane_044 */

#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_09_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_09_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_09_RESETVAL (0x00000058u)

#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_08_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_08_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_08_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_07_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_07_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_07_RESETVAL (0x000000BDu)

#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_06_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_06_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_044_UNDEFINED_06_RESETVAL (0x00000095u)

#define CSL_WIZ8B8SB_COMLANE_044_RESETVAL (0x5803BD95u)

/* comlane_048 */

#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_13_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_13_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_13_RESETVAL (0x00000034u)

#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_12_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_12_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_12_RESETVAL (0x000000C5u)

#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_11_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_11_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_11_RESETVAL (0x000000D0u)

#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_10_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_10_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_048_UNDEFINED_10_RESETVAL (0x000000C9u)

#define CSL_WIZ8B8SB_COMLANE_048_RESETVAL (0x34C5D0C9u)

/* comlane_04c */

#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_17_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_17_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_17_RESETVAL (0x000000A0u)

#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_16_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_16_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_16_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_15_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_15_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_15_RESETVAL (0x00000087u)

#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_14_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_14_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_04C_UNDEFINED_14_RESETVAL (0x0000000Bu)

#define CSL_WIZ8B8SB_COMLANE_04C_RESETVAL (0xA002870Bu)

/* comlane_050 */

#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_21_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_21_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_21_RESETVAL (0x00000051u)

#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_20_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_20_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_20_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_19_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_19_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_19_RESETVAL (0x00000098u)

#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_18_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_18_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_050_UNDEFINED_18_RESETVAL (0x0000000Au)

#define CSL_WIZ8B8SB_COMLANE_050_RESETVAL (0x510F980Au)

/* comlane_054 */

#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_25_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_25_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_25_RESETVAL (0x00000040u)

#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_24_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_24_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_24_RESETVAL (0x0000002Eu)

#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_23_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_23_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_23_RESETVAL (0x0000004Eu)

#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_22_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_22_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_054_UNDEFINED_22_RESETVAL (0x00000082u)

#define CSL_WIZ8B8SB_COMLANE_054_RESETVAL (0x402E4E82u)

/* comlane_058 */

#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_29_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_29_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_29_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_28_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_28_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_28_RESETVAL (0x0000002Du)

#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_27_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_27_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_27_RESETVAL (0x00000011u)

#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_26_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_26_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_058_UNDEFINED_26_RESETVAL (0x0000007Au)

#define CSL_WIZ8B8SB_COMLANE_058_RESETVAL (0x002D117Au)

/* comlane_05c */

#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_33_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_33_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_33_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_32_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_32_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_32_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_31_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_31_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_31_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_30_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_30_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_05C_UNDEFINED_30_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_05C_RESETVAL (0x00000000u)

/* comlane_060 */

#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_37_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_37_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_37_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_36_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_36_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_36_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_35_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_35_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_35_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_34_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_34_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_060_UNDEFINED_34_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_060_RESETVAL (0x00000000u)

/* comlane_064 */

#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_41_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_41_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_41_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_40_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_40_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_40_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_39_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_39_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_39_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_38_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_38_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_064_UNDEFINED_38_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_064_RESETVAL (0x00000000u)

/* comlane_068 */

#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_45_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_45_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_45_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_44_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_44_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_44_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_43_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_43_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_43_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_42_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_42_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_068_UNDEFINED_42_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_068_RESETVAL (0x00000000u)

/* comlane_06c */

#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_49_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_49_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_49_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_48_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_48_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_48_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_47_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_47_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_47_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_46_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_46_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_06C_UNDEFINED_46_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_06C_RESETVAL (0x00000000u)

/* comlane_070 */

#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_53_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_53_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_53_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_52_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_52_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_52_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_51_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_51_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_51_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_50_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_50_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_070_UNDEFINED_50_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_070_RESETVAL (0x00000000u)

/* comlane_074 */

#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_57_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_57_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_57_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_56_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_56_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_56_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_55_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_55_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_55_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_54_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_54_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_074_UNDEFINED_54_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_074_RESETVAL (0x00000000u)

/* comlane_078 */

#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_61_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_61_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_61_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_60_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_60_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_60_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_59_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_59_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_59_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_58_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_58_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_078_UNDEFINED_58_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_078_RESETVAL (0x00000000u)

/* comlane_07c */

#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_66_MASK (0xF8000000u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_66_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_66_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_07C_QAHB_CDR_VCO_CAL_PHD_ENA_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_07C_QAHB_CDR_VCO_CAL_PHD_ENA_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_07C_QAHB_CDR_VCO_CAL_PHD_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_65_MASK (0x03000000u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_65_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_65_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_64_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_64_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_64_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_63_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_63_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_63_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_62_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_62_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_07C_UNDEFINED_62_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_07C_RESETVAL (0x00000000u)

/* comlane_080 */

#define CSL_WIZ8B8SB_COMLANE_080_TXDP_IDLE_IN_DELAY_MASK (0x03000000u)
#define CSL_WIZ8B8SB_COMLANE_080_TXDP_IDLE_IN_DELAY_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_080_TXDP_IDLE_IN_DELAY_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_11_O_1_0_MASK (0x00600000u)
#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_11_O_1_0_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_11_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_01_O_1_0_MASK (0x00180000u)
#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_01_O_1_0_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_01_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_00_O_1_0_MASK (0x00060000u)
#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_00_O_1_0_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_080_TX_PREDRV_SR_00_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_11_O_2_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_11_O_2_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_11_O_2_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_11_O_1_0_MASK (0x0000C000u)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_11_O_1_0_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_11_O_1_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_01_O_2_0_MASK (0x00003800u)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_01_O_2_0_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_01_O_2_0_RESETVAL (0x00000007u)

#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_00_O_2_0_MASK (0x00000700u)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_00_O_2_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_080_RX_BIAS_00_O_2_0_RESETVAL (0x00000007u)

#define CSL_WIZ8B8SB_COMLANE_080_UNDEFINED_67_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_080_UNDEFINED_67_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_080_UNDEFINED_67_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_080_RESETVAL (0x0001FF00u)

/* comlane_084 */

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_ATT_CYCLE_LEN_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_ATT_CYCLE_LEN_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_ATT_CYCLE_LEN_O_3_0_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_14_11_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_14_11_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_14_11_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_10_3_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_10_3_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_10_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_2_0_MASK (0x0000E000u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_2_0_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_CONT_LENGTH_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_PRESET_CLR_DFE_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_PRESET_CLR_DFE_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_PRESET_CLR_DFE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_PRESET_EN_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_PRESET_EN_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_PRESET_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE3_CAL_EN_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE3_CAL_EN_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE3_CAL_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE2_CAL_EN_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE2_CAL_EN_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE2_CAL_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE1_CAL_EN_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE1_CAL_EN_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE1_CAL_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE_CHNG_CAL_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE_CHNG_CAL_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_RATE_CHNG_CAL_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_6_5_MASK (0x00000060u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_6_5_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_6_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_4_1_MASK (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_4_1_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_4_1_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_0_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_084_RXEQ_INIT_CAL_O_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_084_RESETVAL (0xF0000783u)

/* comlane_088 */

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP3_CYCLE_LEN_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP3_CYCLE_LEN_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP3_CYCLE_LEN_O_3_0_RESETVAL (0x0000000Cu)

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP2_CYCLE_LEN_O_7_4_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP2_CYCLE_LEN_O_7_4_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP2_CYCLE_LEN_O_7_4_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP2_CYCLE_LEN_O_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP2_CYCLE_LEN_O_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP2_CYCLE_LEN_O_3_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP1_CYCLE_LEN_O_7_4_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP1_CYCLE_LEN_O_7_4_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP1_CYCLE_LEN_O_7_4_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP1_CYCLE_LEN_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP1_CYCLE_LEN_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_TAP1_CYCLE_LEN_O_3_0_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_BOOST_CYCLE_LEN_O_7_4_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_BOOST_CYCLE_LEN_O_7_4_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_BOOST_CYCLE_LEN_O_7_4_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_BOOST_CYCLE_LEN_O_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_BOOST_CYCLE_LEN_O_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_BOOST_CYCLE_LEN_O_3_0_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_ATT_CYCLE_LEN_O_7_4_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_ATT_CYCLE_LEN_O_7_4_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_088_RXEQ_ATT_CYCLE_LEN_O_7_4_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_088_RESETVAL (0xCF3FFFFFu)

/* comlane_08c */

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_RATE2_INIT_CAL_O_0_0_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_RATE2_INIT_CAL_O_0_0_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_RATE2_INIT_CAL_O_0_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_RECAL_O_6_0_MASK (0x7F000000u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_RECAL_O_6_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_RECAL_O_6_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_08C_TBUS_DFE_CMP_SEL_O_2_0_MASK (0x00E00000u)
#define CSL_WIZ8B8SB_COMLANE_08C_TBUS_DFE_CMP_SEL_O_2_0_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_08C_TBUS_DFE_CMP_SEL_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_EI_EXIT_CAL_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_EI_EXIT_CAL_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_EI_EXIT_CAL_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP5_CYCLE_LEN_O_7_4_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP5_CYCLE_LEN_O_7_4_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP5_CYCLE_LEN_O_7_4_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP5_CYCLE_LEN_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP5_CYCLE_LEN_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP5_CYCLE_LEN_O_3_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP4_CYCLE_LEN_O_7_4_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP4_CYCLE_LEN_O_7_4_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP4_CYCLE_LEN_O_7_4_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP4_CYCLE_LEN_O_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP4_CYCLE_LEN_O_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP4_CYCLE_LEN_O_3_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP3_CYCLE_LEN_O_7_4_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP3_CYCLE_LEN_O_7_4_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_08C_RXEQ_TAP3_CYCLE_LEN_O_7_4_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_08C_RESETVAL (0x8313232Fu)

/* comlane_090 */

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_TAP1_BOUNCE_O_3_0_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_TAP1_BOUNCE_O_3_0_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_TAP1_BOUNCE_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_BOOST_BOUNCE_O_3_0_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_BOOST_BOUNCE_O_3_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_BOOST_BOUNCE_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_ATT_BOUNCE_O_3_0_MASK (0x00F00000u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_ATT_BOUNCE_O_3_0_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_ATT_BOUNCE_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_RECAL_O_6_3_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_RECAL_O_6_3_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_RECAL_O_6_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_RECAL_O_2_0_MASK (0x0000E000u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_RECAL_O_2_0_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_RECAL_O_2_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_CONT_CAL_O_6_2_MASK (0x00001F00u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_CONT_CAL_O_6_2_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_CONT_CAL_O_6_2_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_CONT_CAL_O_1_0_MASK (0x000000C0u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_CONT_CAL_O_1_0_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_CONT_CAL_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_INIT_CAL_O_6_1_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_INIT_CAL_O_6_1_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_090_RXEQ_RATE2_INIT_CAL_O_6_1_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_090_RESETVAL (0x55502000u)

/* comlane_094 */

#define CSL_WIZ8B8SB_COMLANE_094_CDR_CTRL_SIGDET_LOW_MIN_O_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_094_CDR_CTRL_SIGDET_LOW_MIN_O_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_094_CDR_CTRL_SIGDET_LOW_MIN_O_7_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP5_BOUNCE_O_3_0_MASK (0x0000F000u)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP5_BOUNCE_O_3_0_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP5_BOUNCE_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP4_BOUNCE_O_3_0_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP4_BOUNCE_O_3_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP4_BOUNCE_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP3_BOUNCE_O_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP3_BOUNCE_O_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP3_BOUNCE_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP2_BOUNCE_O_3_0_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP2_BOUNCE_O_3_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_094_RXEQ_TAP2_BOUNCE_O_3_0_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_094_RESETVAL (0x01005555u)

/* comlane_098 */

#define CSL_WIZ8B8SB_COMLANE_098_CMP_OFFSET_OVR_EN_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_098_CMP_OFFSET_OVR_EN_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_098_CMP_OFFSET_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_098_RXEQ_FORCE_CAL_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_098_RXEQ_FORCE_CAL_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_098_RXEQ_FORCE_CAL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_098_RXEQ_COARSE_STEP_SIZE_O_3_0_MASK (0x00000078u)
#define CSL_WIZ8B8SB_COMLANE_098_RXEQ_COARSE_STEP_SIZE_O_3_0_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_098_RXEQ_COARSE_STEP_SIZE_O_3_0_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_COMLANE_098_LN_REFCLKDIV_EN_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_098_LN_REFCLKDIV_EN_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_098_LN_REFCLKDIV_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_098_LN_CMUREF_EN_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_098_LN_CMUREF_EN_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_098_LN_CMUREF_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_098_CDR_CTRL_SIGDET_LOW_MIN_O_8_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_098_CDR_CTRL_SIGDET_LOW_MIN_O_8_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_098_CDR_CTRL_SIGDET_LOW_MIN_O_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_098_RESETVAL (0x00000020u)

/* comlane_09c */

#define CSL_WIZ8B8SB_COMLANE_09C_CMP_OFFSET_OVR_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_09C_CMP_OFFSET_OVR_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_09C_CMP_OFFSET_OVR_O_7_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_09C_RESETVAL (0x00000000u)

/* comlane_0a0 */

#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_ERR_SIGN_O_1_0_MASK (0xC0000000u)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_ERR_SIGN_O_1_0_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_ERR_SIGN_O_1_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_LOW_O_6_1_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_LOW_O_6_1_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_LOW_O_6_1_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_LOW_O_0_0_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_LOW_O_0_0_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_LOW_O_0_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_HIGH_O_6_0_MASK (0x007F0000u)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_HIGH_O_6_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0A0_RXEQ_FIN_HIGH_O_6_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0A0_RESETVAL (0x80000000u)

/* comlane_0a4 */

#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP2_TRAINING_PATT_O_8_1_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP2_TRAINING_PATT_O_8_1_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP2_TRAINING_PATT_O_8_1_RESETVAL (0x000000ADu)

#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP2_TRAINING_PATT_O_0_0_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP2_TRAINING_PATT_O_0_0_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP2_TRAINING_PATT_O_0_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP1_TRAINING_PATT_O_8_2_MASK (0x007F0000u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP1_TRAINING_PATT_O_8_2_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP1_TRAINING_PATT_O_8_2_RESETVAL (0x00000052u)

#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP1_TRAINING_PATT_O_1_0_MASK (0x0000C000u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP1_TRAINING_PATT_O_1_0_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_TAP1_TRAINING_PATT_O_1_0_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_3_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_3_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_3_RESETVAL (0x00000028u)

#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_RATE1_BOOST_TRAINING_PATT_O_2_0_MASK (0x000000E0u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_RATE1_BOOST_TRAINING_PATT_O_2_0_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_RATE1_BOOST_TRAINING_PATT_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_ERR_SIGN_O_6_2_MASK (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_ERR_SIGN_O_6_2_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0A4_RXEQ_ERR_SIGN_O_6_2_RESETVAL (0x00000015u)

#define CSL_WIZ8B8SB_COMLANE_0A4_RESETVAL (0xAD52A815u)

/* comlane_0a8 */

#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_DONT_CARE_O_4_0_MASK (0xF8000000u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_DONT_CARE_O_4_0_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_DONT_CARE_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP5_TRAINING_PATT_O_8_6_MASK (0x07000000u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP5_TRAINING_PATT_O_8_6_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP5_TRAINING_PATT_O_8_6_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP5_TRAINING_PATT_O_5_0_MASK (0x00FC0000u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP5_TRAINING_PATT_O_5_0_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP5_TRAINING_PATT_O_5_0_RESETVAL (0x00000014u)

#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP4_TRAINING_PATT_O_8_7_MASK (0x00030000u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP4_TRAINING_PATT_O_8_7_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP4_TRAINING_PATT_O_8_7_RESETVAL (0x00000002u)

#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP4_TRAINING_PATT_O_6_0_MASK (0x0000FE00u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP4_TRAINING_PATT_O_6_0_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP4_TRAINING_PATT_O_6_0_RESETVAL (0x00000056u)

#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP3_TRAINING_PATT_O_8_8_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP3_TRAINING_PATT_O_8_8_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP3_TRAINING_PATT_O_8_8_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP3_TRAINING_PATT_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP3_TRAINING_PATT_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0A8_RXEQ_TAP3_TRAINING_PATT_O_7_0_RESETVAL (0x00000052u)

#define CSL_WIZ8B8SB_COMLANE_0A8_RESETVAL (0x0552AD52u)

/* comlane_0ac */

#define CSL_WIZ8B8SB_COMLANE_0AC_UNDEFINED_69_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_0AC_UNDEFINED_69_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0AC_UNDEFINED_69_RESETVAL (0x00000029u)

#define CSL_WIZ8B8SB_COMLANE_0AC_UNDEFINED_68_MASK (0x00C00000u)
#define CSL_WIZ8B8SB_COMLANE_0AC_UNDEFINED_68_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_COMLANE_0AC_UNDEFINED_68_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_SHIFT_O_3_3_MASK (0x00200000u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_SHIFT_O_3_3_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_SHIFT_O_3_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_SHIFT_O_2_0_MASK (0x001C0000u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_SHIFT_O_2_0_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_SHIFT_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_CONT_CAL_O_6_5_MASK (0x00030000u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_CONT_CAL_O_6_5_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_CONT_CAL_O_6_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_CONT_CAL_O_4_0_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_CONT_CAL_O_4_0_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_CONT_CAL_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_FLOOR_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_FLOOR_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_FLOOR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_AVG4_O_6_5_MASK (0x00000300u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_AVG4_O_6_5_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_AVG4_O_6_5_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_AVG4_O_4_0_MASK (0x000000F8u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_AVG4_O_4_0_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_AVG4_O_4_0_RESETVAL (0x0000001Fu)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_STEP_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_STEP_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_STEP_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_STEP_MODE_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_STEP_MODE_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_STEP_MODE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_DONT_CARE_O_5_5_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_DONT_CARE_O_5_5_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0AC_RXEQ_DONT_CARE_O_5_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0AC_RESETVAL (0x290003F8u)

/* comlane_0b0 */

#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_73_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_73_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_73_RESETVAL (0x00000008u)

#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_72_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_72_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_72_RESETVAL (0x00000020u)

#define CSL_WIZ8B8SB_COMLANE_0B0_RXEQ_RATE2_TAP2_START_O_0_0_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_0B0_RXEQ_RATE2_TAP2_START_O_0_0_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_0B0_RXEQ_RATE2_TAP2_START_O_0_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_71_MASK (0x00007F00u)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_71_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_71_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_70_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_70_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0B0_UNDEFINED_70_RESETVAL (0x0000006Bu)

#define CSL_WIZ8B8SB_COMLANE_0B0_RESETVAL (0x0820816Bu)

/* comlane_0b4 */

#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_77_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_77_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_77_RESETVAL (0x00000010u)

#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_76_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_76_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_76_RESETVAL (0x00000040u)

#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE3_TAP1_START_O_0_0_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE3_TAP1_START_O_0_0_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE3_TAP1_START_O_0_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_75_MASK (0x00007F00u)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_75_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_75_RESETVAL (0x00000017u)

#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE3_ATT_START_O_0_0_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE3_ATT_START_O_0_0_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE3_ATT_START_O_0_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_74_MASK (0x0000007Eu)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_74_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_0B4_UNDEFINED_74_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE2_TAP4_START_O_5_5_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE2_TAP4_START_O_5_5_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0B4_RXEQ_RATE2_TAP4_START_O_5_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0B4_RESETVAL (0x10409782u)

/* comlane_0b8 */

#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_MASK_O_14_7_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_MASK_O_14_7_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_MASK_O_14_7_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_MASK_O_6_0_MASK (0x00FE0000u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_MASK_O_6_0_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_MASK_O_6_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_SHIFT_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_SHIFT_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_SHIFT_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_RUN_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_RUN_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_RUN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_COUNTER_EN_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_COUNTER_EN_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_0B8_EYE_SCAN_COUNTER_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0B8_UNDEFINED_79_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_COMLANE_0B8_UNDEFINED_79_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0B8_UNDEFINED_79_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0B8_UNDEFINED_78_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_0B8_UNDEFINED_78_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0B8_UNDEFINED_78_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_COMLANE_0B8_RESETVAL (0x00000104u)

/* comlane_0bc */

#define CSL_WIZ8B8SB_COMLANE_0BC_RXEQ_RATE2_DFE_TAP_PD_O_2_0_MASK (0xE0000000u)
#define CSL_WIZ8B8SB_COMLANE_0BC_RXEQ_RATE2_DFE_TAP_PD_O_2_0_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_0BC_RXEQ_RATE2_DFE_TAP_PD_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0BC_RXEQ_RATE3_DFE_TAP_PD_O_4_0_MASK (0x1F000000u)
#define CSL_WIZ8B8SB_COMLANE_0BC_RXEQ_RATE3_DFE_TAP_PD_O_4_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0BC_RXEQ_RATE3_DFE_TAP_PD_O_4_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_15_12_MASK (0x000F0000u)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_15_12_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_15_12_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_11_4_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_11_4_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_11_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_3_0_MASK (0x000000F0u)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_3_0_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_WAIT_LEN_O_3_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_MASK_O_18_15_MASK (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_MASK_O_18_15_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0BC_EYE_SCAN_MASK_O_18_15_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0BC_RESETVAL (0x00000000u)

/* comlane_0c0 */

#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_3_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_3_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_3_RESETVAL (0x00000028u)

#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_BOOST_TRAINING_PATT_O_2_0_MASK (0x00070000u)
#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_BOOST_TRAINING_PATT_O_2_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_BOOST_TRAINING_PATT_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0C0_UNDEFINED_81_MASK (0x0000FC00u)
#define CSL_WIZ8B8SB_COMLANE_0C0_UNDEFINED_81_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_0C0_UNDEFINED_81_RESETVAL (0x0000003Eu)

#define CSL_WIZ8B8SB_COMLANE_0C0_DFE_TAP_OFFSET_CAL_DIR_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_0C0_DFE_TAP_OFFSET_CAL_DIR_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_0C0_DFE_TAP_OFFSET_CAL_DIR_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0C0_SKP_CMP_CAL_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_0C0_SKP_CMP_CAL_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0C0_SKP_CMP_CAL_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0C0_UNDEFINED_80_MASK (0x000000F8u)
#define CSL_WIZ8B8SB_COMLANE_0C0_UNDEFINED_80_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_0C0_UNDEFINED_80_RESETVAL (0x00000011u)

#define CSL_WIZ8B8SB_COMLANE_0C0_REVERSE_TAP_PD_ORDER_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_0C0_REVERSE_TAP_PD_ORDER_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_0C0_REVERSE_TAP_PD_ORDER_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_DFE_TAP_PD_O_4_3_MASK (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_DFE_TAP_PD_O_4_3_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0C0_RXEQ_RATE2_DFE_TAP_PD_O_4_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0C0_RESETVAL (0x2800FA88u)

/* comlane_0c4 */

#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_MASK (0x003F0000u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_3_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_3_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_3_RESETVAL (0x00000028u)

#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE3_BOOST_TRAINING_PATT_O_2_0_MASK (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE3_BOOST_TRAINING_PATT_O_2_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0C4_RXEQ_RATE3_BOOST_TRAINING_PATT_O_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0C4_RESETVAL (0x01002800u)

/* comlane_0c8 */

#define CSL_WIZ8B8SB_COMLANE_0C8_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_COMLANE_0C8_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0C8_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0C8_RESETVAL (0x00000000u)

/* comlane_0e8 */

#define CSL_WIZ8B8SB_COMLANE_0E8_UNDEFINED_82_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_0E8_UNDEFINED_82_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0E8_UNDEFINED_82_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_0E8_RESETVAL (0x03000000u)

/* comlane_0ec */

#define CSL_WIZ8B8SB_COMLANE_0EC_TAP1_CM1_TRAINING_PATT_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_0EC_TAP1_CM1_TRAINING_PATT_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0EC_TAP1_CM1_TRAINING_PATT_7_0_RESETVAL (0x00000054u)

#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_TXEQ_RXRECAL_END_CFG_6_0_MASK (0x007F0000u)
#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_TXEQ_RXRECAL_END_CFG_6_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_TXEQ_RXRECAL_END_CFG_6_0_RESETVAL (0x0000001Fu)

#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_MASK (0x00007F00u)
#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_RESETVAL (0x00000040u)

#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_RATESWITCH_RXRECAL_CFG_6_0_MASK (0x0000007Fu)
#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_RATESWITCH_RXRECAL_CFG_6_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0EC_RATE3_RATESWITCH_RXRECAL_CFG_6_0_RESETVAL (0x00000003u)

#define CSL_WIZ8B8SB_COMLANE_0EC_RESETVAL (0x541F4003u)

/* comlane_0f0 */

#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_SHADOW_OFST_RD_SEL_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_SHADOW_OFST_RD_SEL_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_SHADOW_OFST_RD_SEL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_SHADOW_LANE_SEL_MASK (0x0C000000u)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_SHADOW_LANE_SEL_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_SHADOW_LANE_SEL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_TAP_CMP_NO_OFST_OVR_EN_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_TAP_CMP_NO_OFST_OVR_EN_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_TAP_CMP_NO_OFST_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_TAP_OVR_EN_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_TAP_OVR_EN_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0F0_DFE_TAP_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_C1_TRAINING_PATT_8_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_C1_TRAINING_PATT_8_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_C1_TRAINING_PATT_8_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_C1_TRAINING_PATT_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_C1_TRAINING_PATT_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_C1_TRAINING_PATT_7_0_RESETVAL (0x000000A5u)

#define CSL_WIZ8B8SB_COMLANE_0F0_UNDEFINED_83_MASK (0x000000FEu)
#define CSL_WIZ8B8SB_COMLANE_0F0_UNDEFINED_83_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_0F0_UNDEFINED_83_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_CM1_TRAINING_PATT_8_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_CM1_TRAINING_PATT_8_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0F0_TAP1_CM1_TRAINING_PATT_8_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_0F0_RESETVAL (0x0000A501u)

/* comlane_0f4 */

#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_87_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_87_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_87_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_86_MASK (0x003F0000u)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_86_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_86_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_85_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_85_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_85_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_84_MASK (0x0000007Fu)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_84_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0F4_UNDEFINED_84_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F4_RESETVAL (0x00000000u)

/* comlane_0f8 */

#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_TAP2_VAL_MASK (0x3F000000u)
#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_TAP2_VAL_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_TAP2_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_TAP1_VAL_MASK (0x007F0000u)
#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_TAP1_VAL_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_TAP1_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_CMP_VAL_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_CMP_VAL_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0F8_DFE_CMP_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F8_UNDEFINED_88_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_COMLANE_0F8_UNDEFINED_88_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0F8_UNDEFINED_88_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0F8_RESETVAL (0x00000000u)

/* comlane_0fc */

#define CSL_WIZ8B8SB_COMLANE_0FC_UNDEFINED_89_MASK (0xF8000000u)
#define CSL_WIZ8B8SB_COMLANE_0FC_UNDEFINED_89_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_0FC_UNDEFINED_89_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_CMP_CAL_EN_OVR_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_CMP_CAL_EN_OVR_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_CMP_CAL_EN_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_OFFSET_CAL_EN_OVR_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_OFFSET_CAL_EN_OVR_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_OFFSET_CAL_EN_OVR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_OFFSET_CAL_VAL_OVR_EN_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_OFFSET_CAL_VAL_OVR_EN_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_OFFSET_CAL_VAL_OVR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP5_VAL_MASK (0x003F0000u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP5_VAL_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP5_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP4_VAL_MASK (0x00003F00u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP4_VAL_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP4_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP3_VAL_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP3_VAL_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_0FC_DFE_TAP3_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_0FC_RESETVAL (0x00000000u)

/* comlane_100 */

#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_93_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_93_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_93_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_92_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_92_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_92_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_91_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_91_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_91_RESETVAL (0x000000A5u)

#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_90_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_90_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_100_UNDEFINED_90_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_100_RESETVAL (0x0000A500u)

/* comlane_104 */

#define CSL_WIZ8B8SB_COMLANE_104_TXTERM_CAL_LN_SEL_O_1_0_MASK (0x06000000u)
#define CSL_WIZ8B8SB_COMLANE_104_TXTERM_CAL_LN_SEL_O_1_0_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_104_TXTERM_CAL_LN_SEL_O_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_104_TXTERM_CAL_SEQ_EN_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_104_TXTERM_CAL_SEQ_EN_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_104_TXTERM_CAL_SEQ_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_96_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_96_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_96_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_95_MASK (0x00000300u)
#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_95_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_95_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_94_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_94_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_104_UNDEFINED_94_RESETVAL (0x00000005u)

#define CSL_WIZ8B8SB_COMLANE_104_RESETVAL (0x00000005u)

/* comlane_108 */

#define CSL_WIZ8B8SB_COMLANE_108_MSM_SAPI_PARTIAL_TO_NORM_DELAY_O_7_0_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_SAPI_PARTIAL_TO_NORM_DELAY_O_7_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_SAPI_PARTIAL_TO_NORM_DELAY_O_7_0_RESETVAL (0x00000087u)

#define CSL_WIZ8B8SB_COMLANE_108_MSM_SAPI_START_DELAY_O_7_0_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_SAPI_START_DELAY_O_7_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_SAPI_START_DELAY_O_7_0_RESETVAL (0x0000004Fu)

#define CSL_WIZ8B8SB_COMLANE_108_MSM_PIPE_P1_TO_P0_DELAY_O_7_0_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_PIPE_P1_TO_P0_DELAY_O_7_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_PIPE_P1_TO_P0_DELAY_O_7_0_RESETVAL (0x00000058u)

#define CSL_WIZ8B8SB_COMLANE_108_MSM_PIPE_START_DELAY_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_PIPE_START_DELAY_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_108_MSM_PIPE_START_DELAY_O_7_0_RESETVAL (0x00000033u)

#define CSL_WIZ8B8SB_COMLANE_108_RESETVAL (0x874F5833u)

/* comlane_10c */

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_RST_SPARE1_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_RST_SPARE1_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_TXREG_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_TXREG_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_TXREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_TXREG_BLEED_ENA_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_TXREG_BLEED_ENA_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_TXREG_BLEED_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_TXDRV_LP_IDLE_ENA_O_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_TXDRV_LP_IDLE_ENA_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RX_CLK_EN_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RX_CLK_EN_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RX_CLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDR_EN_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDR_EN_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDR_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_IDDQ_SD_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_IDDQ_SD_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_DFE_BIAS_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_DFE_BIAS_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_DFE_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_VCO_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_VCO_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_TXDRV_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_TXDRV_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_SLV_BIAS_O_MASK (0x00200000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_SLV_BIAS_O_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_S2P_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_S2P_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_S2P_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_RA_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_RA_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_RA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_P2S_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_P2S_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_P2S_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_LNREG_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_LNREG_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_LNREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_DFE_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_DFE_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_PD_DFE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDN_RX_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDN_RX_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDN_RX_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDN_TX_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDN_TX_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_CDN_TX_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_LANEREG_O_MASK (0x00002000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_LANEREG_O_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_LANEREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_RA_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_RA_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_RA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_VCO_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_VCO_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_TXDRV_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_TXDRV_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_DFE_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_DFE_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_DFE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_CDR_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_CDR_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_PIPE_P0_RESET_CDR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_10C_MSM_SAPI_RST_TO_NORM_DELAY_O_7_0_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_SAPI_RST_TO_NORM_DELAY_O_7_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_10C_MSM_SAPI_RST_TO_NORM_DELAY_O_7_0_RESETVAL (0x0000005Fu)

#define CSL_WIZ8B8SB_COMLANE_10C_RESETVAL (0x0400C05Fu)

/* comlane_110 */

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_CDN_RX_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_CDN_RX_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_CDN_RX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_CDN_TX_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_CDN_TX_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_CDN_TX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_LANEREG_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_LANEREG_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_LANEREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_RA_O_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_RA_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_VCO_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_VCO_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_VCO_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_TXDRV_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_TXDRV_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_TXDRV_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_DFE_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_DFE_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_CDR_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_CDR_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P2_RESET_CDR_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_RST_SPARE1_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_RST_SPARE1_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_TXREG_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_TXREG_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_TXREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_TXREG_BLEED_ENA_O_MASK (0x00200000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_TXREG_BLEED_ENA_O_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_TXREG_BLEED_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_TXDRV_LP_IDLE_ENA_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_TXDRV_LP_IDLE_ENA_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RX_CLK_EN_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RX_CLK_EN_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RX_CLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDR_EN_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDR_EN_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_IDDQ_SD_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_IDDQ_SD_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_DFE_BIAS_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_DFE_BIAS_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_DFE_BIAS_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_VCO_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_VCO_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_TXDRV_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_TXDRV_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_SLV_BIAS_O_MASK (0x00002000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_SLV_BIAS_O_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_S2P_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_S2P_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_S2P_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_RA_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_RA_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_P2S_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_P2S_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_P2S_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_LNREG_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_LNREG_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_LNREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_DFE_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_DFE_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_PD_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDN_RX_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDN_RX_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDN_RX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDN_TX_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDN_TX_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_CDN_TX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_LANEREG_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_LANEREG_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_LANEREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_RA_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_RA_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_RA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_VCO_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_VCO_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_TXDRV_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_TXDRV_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_DFE_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_DFE_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_DFE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_CDR_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_CDR_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_110_MSM_PIPE_P1_RESET_CDR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_110_RESETVAL (0x3F011D00u)

/* comlane_114 */

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_VCO_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_VCO_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_TXDRV_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_TXDRV_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_SLV_BIAS_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_SLV_BIAS_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_S2P_O_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_S2P_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_S2P_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_RA_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_RA_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_P2S_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_P2S_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_P2S_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_LNREG_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_LNREG_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_LNREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_DFE_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_DFE_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_PD_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_CDN_RX_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_CDN_RX_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_CDN_RX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_CDN_TX_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_CDN_TX_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_CDN_TX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_LANEREG_O_MASK (0x00200000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_LANEREG_O_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_LANEREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_RA_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_RA_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_VCO_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_VCO_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_VCO_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_TXDRV_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_TXDRV_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_TXDRV_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_DFE_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_DFE_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_CDR_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_CDR_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_RST_RESET_CDR_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_RST_SPARE1_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_RST_SPARE1_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_TXREG_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_TXREG_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_TXREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_TXREG_BLEED_ENA_O_MASK (0x00002000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_TXREG_BLEED_ENA_O_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_TXREG_BLEED_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_TXDRV_LP_IDLE_ENA_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_TXDRV_LP_IDLE_ENA_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_RX_CLK_EN_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_RX_CLK_EN_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_RX_CLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_CDR_EN_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_CDR_EN_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_CDR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_IDDQ_SD_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_IDDQ_SD_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_DFE_BIAS_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_DFE_BIAS_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_DFE_BIAS_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_VCO_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_VCO_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_VCO_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_TXDRV_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_TXDRV_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_TXDRV_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_SLV_BIAS_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_SLV_BIAS_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_S2P_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_S2P_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_S2P_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_RA_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_RA_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_P2S_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_P2S_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_P2S_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_LNREG_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_LNREG_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_LNREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_DFE_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_DFE_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_114_MSM_PIPE_P2_PD_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_114_RESETVAL (0x1D3F71DFu)

/* comlane_118 */

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_RST_SPARE1_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_RST_SPARE1_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_TXREG_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_TXREG_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_TXREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_TXDRV_LP_IDLE_ENA_O_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_TXDRV_LP_IDLE_ENA_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RX_CLK_EN_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RX_CLK_EN_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RX_CLK_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDR_EN_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDR_EN_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDR_EN_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_IDDQ_SD_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_IDDQ_SD_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_DFE_BIAS_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_DFE_BIAS_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_DFE_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_VCO_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_VCO_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_TXDRV_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_TXDRV_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_SLV_BIAS_O_MASK (0x00200000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_SLV_BIAS_O_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_S2P_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_S2P_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_S2P_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_RA_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_RA_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_RA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_P2S_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_P2S_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_P2S_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_LNREG_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_LNREG_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_LNREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_DFE_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_DFE_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_PD_DFE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDN_RX_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDN_RX_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDN_RX_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDN_TX_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDN_TX_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_CDN_TX_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_LANEREG_O_MASK (0x00002000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_LANEREG_O_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_LANEREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_RA_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_RA_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_RA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_VCO_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_VCO_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_TXDRV_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_TXDRV_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_DFE_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_DFE_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_DFE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_CDR_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_CDR_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_SAPI_NORM_RESET_CDR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_RST_SPARE1_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_RST_SPARE1_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_TXREG_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_TXREG_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_TXREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_TXREG_BLEED_ENA_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_TXREG_BLEED_ENA_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_TXREG_BLEED_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_TXDRV_LP_IDLE_ENA_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_TXDRV_LP_IDLE_ENA_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_RX_CLK_EN_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_RX_CLK_EN_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_RX_CLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_CDR_EN_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_CDR_EN_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_CDR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_IDDQ_SD_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_IDDQ_SD_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_DFE_BIAS_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_DFE_BIAS_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_118_MSM_PIPE_RST_PD_DFE_BIAS_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_118_RESETVAL (0x0C00C031u)

/* comlane_11c */

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_CDN_RX_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_CDN_RX_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_CDN_RX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_CDN_TX_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_CDN_TX_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_CDN_TX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_LANEREG_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_LANEREG_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_LANEREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_RA_O_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_RA_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_VCO_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_VCO_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_VCO_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_TXDRV_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_TXDRV_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_TXDRV_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_DFE_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_DFE_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_CDR_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_CDR_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_SLUMBER_RESET_CDR_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_RST_SPARE1_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_RST_SPARE1_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_TXREG_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_TXREG_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_TXREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_MASK (0x00200000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_TXDRV_LP_IDLE_ENA_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_TXDRV_LP_IDLE_ENA_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RX_CLK_EN_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RX_CLK_EN_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RX_CLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDR_EN_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDR_EN_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_IDDQ_SD_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_IDDQ_SD_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_VCO_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_VCO_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_TXDRV_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_TXDRV_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_MASK (0x00002000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_S2P_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_S2P_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_S2P_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_RA_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_RA_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_P2S_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_P2S_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_P2S_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_LNREG_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_LNREG_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_LNREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_DFE_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_DFE_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_PD_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDN_RX_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDN_RX_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDN_RX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDN_TX_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDN_TX_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_CDN_TX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_LANEREG_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_LANEREG_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_LANEREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_RA_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_RA_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_RA_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_VCO_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_VCO_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_TXDRV_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_TXDRV_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_DFE_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_DFE_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_DFE_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_CDR_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_CDR_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_11C_MSM_SAPI_PARTIAL_RESET_CDR_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_11C_RESETVAL (0x3F011D00u)

/* comlane_120 */

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_VCO_O_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_VCO_O_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_VCO_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_TXDRV_O_MASK (0x40000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_TXDRV_O_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_TXDRV_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_SLV_BIAS_O_MASK (0x20000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_SLV_BIAS_O_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_S2P_O_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_S2P_O_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_S2P_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_RA_O_MASK (0x08000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_RA_O_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_P2S_O_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_P2S_O_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_P2S_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_LNREG_O_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_LNREG_O_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_LNREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_DFE_O_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_DFE_O_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_PD_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_CDN_RX_O_MASK (0x00800000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_CDN_RX_O_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_CDN_RX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_CDN_TX_O_MASK (0x00400000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_CDN_TX_O_SHIFT (0x00000016u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_CDN_TX_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_LANEREG_O_MASK (0x00200000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_LANEREG_O_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_LANEREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_RA_O_MASK (0x00100000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_RA_O_SHIFT (0x00000014u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_VCO_O_MASK (0x00080000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_VCO_O_SHIFT (0x00000013u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_VCO_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_TXDRV_O_MASK (0x00040000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_TXDRV_O_SHIFT (0x00000012u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_TXDRV_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_DFE_O_MASK (0x00020000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_DFE_O_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_CDR_O_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_CDR_O_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_RST_RESET_CDR_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_RST_SPARE1_O_MASK (0x00008000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_RST_SPARE1_O_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_TXREG_O_MASK (0x00004000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_TXREG_O_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_TXREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_MASK (0x00002000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_TXDRV_LP_IDLE_ENA_O_MASK (0x00001000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_TXDRV_LP_IDLE_ENA_O_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_RX_CLK_EN_O_MASK (0x00000800u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_RX_CLK_EN_O_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_RX_CLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_CDR_EN_O_MASK (0x00000400u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_CDR_EN_O_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_CDR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_IDDQ_SD_O_MASK (0x00000200u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_IDDQ_SD_O_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_MASK (0x00000100u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_VCO_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_VCO_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_VCO_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_TXDRV_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_TXDRV_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_TXDRV_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_S2P_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_S2P_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_S2P_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_RA_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_RA_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_RA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_P2S_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_P2S_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_P2S_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_LNREG_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_LNREG_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_LNREG_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_DFE_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_DFE_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_120_MSM_SAPI_SLUMBER_PD_DFE_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_120_RESETVAL (0x1D3F71DFu)

/* comlane_124 */

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_RST_SPARE1_O_MASK (0x00000080u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_RST_SPARE1_O_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_RST_SPARE1_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_TXREG_O_MASK (0x00000040u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_TXREG_O_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_TXREG_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_TXREG_BLEED_ENA_O_MASK (0x00000020u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_TXREG_BLEED_ENA_O_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_TXREG_BLEED_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_TXDRV_LP_IDLE_ENA_O_MASK (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_TXDRV_LP_IDLE_ENA_O_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_TXDRV_LP_IDLE_ENA_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_RX_CLK_EN_O_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_RX_CLK_EN_O_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_RX_CLK_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_CDR_EN_O_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_CDR_EN_O_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_CDR_EN_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_IDDQ_SD_O_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_IDDQ_SD_O_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_IDDQ_SD_O_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_DFE_BIAS_O_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_DFE_BIAS_O_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_124_MSM_SAPI_RST_PD_DFE_BIAS_O_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_124_RESETVAL (0x00000031u)

/* comlane_1f4 */

#define CSL_WIZ8B8SB_COMLANE_1F4_CPU_AHB_CK_RATIO_O_7_4_MASK (0xF0000000u)
#define CSL_WIZ8B8SB_COMLANE_1F4_CPU_AHB_CK_RATIO_O_7_4_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_1F4_CPU_AHB_CK_RATIO_O_7_4_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_100_MASK (0x0F000000u)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_100_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_100_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_99_MASK (0x00030000u)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_99_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_99_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_98_MASK (0x00000F00u)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_98_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_98_RESETVAL (0x0000000Fu)

#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_97_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_97_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_1F4_UNDEFINED_97_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F4_RESETVAL (0xF1000F00u)

/* comlane_1f8 */

#define CSL_WIZ8B8SB_COMLANE_1F8_LN3_OK_I_7_MASK (0x80000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN3_OK_I_7_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN3_OK_I_7_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LN2_OK_I_6_MASK (0x40000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN2_OK_I_6_SHIFT (0x0000001Eu)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN2_OK_I_6_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LN1_OK_I_5_MASK (0x20000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN1_OK_I_5_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN1_OK_I_5_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LN0_OK_I_4_MASK (0x10000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN0_OK_I_4_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN0_OK_I_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LN3_SIG_LEVEL_VALID_I_3_MASK (0x08000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN3_SIG_LEVEL_VALID_I_3_SHIFT (0x0000001Bu)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN3_SIG_LEVEL_VALID_I_3_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LN2_SIG_LEVEL_VALID_I_2_MASK (0x04000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN2_SIG_LEVEL_VALID_I_2_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN2_SIG_LEVEL_VALID_I_2_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LN1_SIG_LEVEL_VALID_I_1_MASK (0x02000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN1_SIG_LEVEL_VALID_I_1_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN1_SIG_LEVEL_VALID_I_1_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LN0_SIG_LEVEL_VALID_I_0_MASK (0x01000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN0_SIG_LEVEL_VALID_I_0_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LN0_SIG_LEVEL_VALID_I_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_CMU_OK_I_0_MASK (0x00010000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_CMU_OK_I_0_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMLANE_1F8_CMU_OK_I_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_MODE_I_2_0_MASK (0x00000700u)
#define CSL_WIZ8B8SB_COMLANE_1F8_MODE_I_2_0_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_1F8_MODE_I_2_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN3_INTRPT_I_3_CLEAR_WRITE_MASK (0x00000008u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN3_INTRPT_I_3_CLEAR_WRITE_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN3_INTRPT_I_3_CLEAR_WRITE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN2_INTRPT_I_2_CLEAR_WRITE_MASK (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN2_INTRPT_I_2_CLEAR_WRITE_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN2_INTRPT_I_2_CLEAR_WRITE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN1_INTRPT_I_1_CLEAR_WRITE_MASK (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN1_INTRPT_I_1_CLEAR_WRITE_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN1_INTRPT_I_1_CLEAR_WRITE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN0_INTRPT_I_0_CLEAR_WRITE_MASK (0x00000001u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN0_INTRPT_I_0_CLEAR_WRITE_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_1F8_LOS_LN0_INTRPT_I_0_CLEAR_WRITE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1F8_RESETVAL (0x00000000u)

/* comlane_1fc */

#define CSL_WIZ8B8SB_COMLANE_1FC_LN3_RX_LOCKED_I_7_6_MASK (0x000000C0u)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN3_RX_LOCKED_I_7_6_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN3_RX_LOCKED_I_7_6_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1FC_LN2_RX_LOCKED_I_5_4_MASK (0x00000030u)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN2_RX_LOCKED_I_5_4_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN2_RX_LOCKED_I_5_4_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1FC_LN1_RX_LOCKED_I_3_2_MASK (0x0000000Cu)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN1_RX_LOCKED_I_3_2_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN1_RX_LOCKED_I_3_2_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1FC_LN0_RX_LOCKED_I_1_0_MASK (0x00000003u)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN0_RX_LOCKED_I_1_0_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMLANE_1FC_LN0_RX_LOCKED_I_1_0_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMLANE_1FC_RESETVAL (0x00000000u)

/* MOD_VER */

#define CSL_WIZ8B8SB_MOD_VER_MODULE_ID_MASK (0xFFFF0000u)
#define CSL_WIZ8B8SB_MOD_VER_MODULE_ID_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_MOD_VER_MODULE_ID_RESETVAL (0x00004EB9u)

#define CSL_WIZ8B8SB_MOD_VER_RTL_VERSION_MASK (0x0000F800u)
#define CSL_WIZ8B8SB_MOD_VER_RTL_VERSION_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_MOD_VER_RTL_VERSION_RESETVAL (0x00000004u)

#define CSL_WIZ8B8SB_MOD_VER_MAJOR_REVISION_MASK (0x00000700u)
#define CSL_WIZ8B8SB_MOD_VER_MAJOR_REVISION_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_MOD_VER_MAJOR_REVISION_RESETVAL (0x00000001u)

#define CSL_WIZ8B8SB_MOD_VER_CUSTOM_REVISION_MASK (0x000000C0u)
#define CSL_WIZ8B8SB_MOD_VER_CUSTOM_REVISION_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_MOD_VER_CUSTOM_REVISION_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_MOD_VER_MINOR_REVISION_MASK (0x0000003Fu)
#define CSL_WIZ8B8SB_MOD_VER_MINOR_REVISION_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_MOD_VER_MINOR_REVISION_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_MOD_VER_RESETVAL    (0x4EB92100u)

/* LANExCTL_STS */

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_ENABLE_OVL_MASK (0x80000000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_ENABLE_OVL_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_ENABLE_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_ENABLE_VAL_MASK (0x60000000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_ENABLE_VAL_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_ENABLE_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_RATE_OVL_MASK (0x10000000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_RATE_OVL_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_RATE_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_RATE_VAL_MASK (0x0C000000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_RATE_VAL_SHIFT (0x0000001Au)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_RATE_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_IDLE_OVL_MASK (0x02000000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_IDLE_OVL_SHIFT (0x00000019u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_IDLE_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_IDLE_VAL_MASK (0x01000000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_IDLE_VAL_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_IDLE_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_WIDTH_OVL_MASK (0x00800000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_WIDTH_OVL_SHIFT (0x00000017u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_WIDTH_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_WIDTH_VAL_MASK (0x00600000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_WIDTH_VAL_SHIFT (0x00000015u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_TX0_WIDTH_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ENABLE_OVL_MASK (0x00008000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ENABLE_OVL_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ENABLE_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ENABLE_VAL_MASK (0x00006000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ENABLE_VAL_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ENABLE_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_RATE_OVL_MASK (0x00001000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_RATE_OVL_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_RATE_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_RATE_VAL_MASK (0x00000C00u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_RATE_VAL_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_RATE_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_POLARITY_OVL_MASK (0x00000200u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_POLARITY_OVL_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_POLARITY_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_POLARITY_VAL_MASK (0x00000100u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_POLARITY_VAL_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_POLARITY_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ALIGN_OVL_MASK (0x00000080u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ALIGN_OVL_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ALIGN_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ALIGN_VAL_MASK (0x00000040u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ALIGN_VAL_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_ALIGN_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_WIDTH_OVL_MASK (0x00000020u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_WIDTH_OVL_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_WIDTH_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_WIDTH_VAL_MASK (0x00000018u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_WIDTH_VAL_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_WIDTH_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_OK_MASK (0x00000002u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_OK_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_OK_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_LOSS_MASK (0x00000001u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_LOSS_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_LANEXCTL_STS_RX0_LOSS_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_LANEXCTL_STS_RESETVAL (0x00000000u)

/* PLL_CTRL */

#define CSL_WIZ8B8SB_PLL_CTRL_PLL_ENABLE_OVL_MASK (0x80000000u)
#define CSL_WIZ8B8SB_PLL_CTRL_PLL_ENABLE_OVL_SHIFT (0x0000001Fu)
#define CSL_WIZ8B8SB_PLL_CTRL_PLL_ENABLE_OVL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_PLL_ENABLE_VAL_MASK (0x60000000u)
#define CSL_WIZ8B8SB_PLL_CTRL_PLL_ENABLE_VAL_SHIFT (0x0000001Du)
#define CSL_WIZ8B8SB_PLL_CTRL_PLL_ENABLE_VAL_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_PLL_OK_MASK (0x10000000u)
#define CSL_WIZ8B8SB_PLL_CTRL_PLL_OK_SHIFT (0x0000001Cu)
#define CSL_WIZ8B8SB_PLL_CTRL_PLL_OK_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN_WAFTER_OK_MASK (0x00020000u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN_WAFTER_OK_SHIFT (0x00000011u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN_WAFTER_OK_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN_WAFTER_SD_MASK (0x00010000u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN_WAFTER_SD_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN_WAFTER_SD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN3_CONT_OK_MASK (0x00008000u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_CONT_OK_SHIFT (0x0000000Fu)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_CONT_OK_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN2_CONT_OK_MASK (0x00004000u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_CONT_OK_SHIFT (0x0000000Eu)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_CONT_OK_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN1_CONT_OK_MASK (0x00002000u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_CONT_OK_SHIFT (0x0000000Du)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_CONT_OK_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN0_CONT_OK_MASK (0x00001000u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_CONT_OK_SHIFT (0x0000000Cu)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_CONT_OK_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN3_OK_STATE_MASK (0x00000800u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_OK_STATE_SHIFT (0x0000000Bu)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_OK_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN2_OK_STATE_MASK (0x00000400u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_OK_STATE_SHIFT (0x0000000Au)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_OK_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN1_OK_STATE_MASK (0x00000200u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_OK_STATE_SHIFT (0x00000009u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_OK_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN0_OK_STATE_MASK (0x00000100u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_OK_STATE_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_OK_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN3_CONT_SD_MASK (0x00000080u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_CONT_SD_SHIFT (0x00000007u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_CONT_SD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN2_CONT_SD_MASK (0x00000040u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_CONT_SD_SHIFT (0x00000006u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_CONT_SD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN1_CONT_SD_MASK (0x00000020u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_CONT_SD_SHIFT (0x00000005u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_CONT_SD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN0_CONT_SD_MASK (0x00000010u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_CONT_SD_SHIFT (0x00000004u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_CONT_SD_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN3_SD_STATE_MASK (0x00000008u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_SD_STATE_SHIFT (0x00000003u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN3_SD_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN2_SD_STATE_MASK (0x00000004u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_SD_STATE_SHIFT (0x00000002u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN2_SD_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN1_SD_STATE_MASK (0x00000002u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_SD_STATE_SHIFT (0x00000001u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN1_SD_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_LN0_SD_STATE_MASK (0x00000001u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_SD_STATE_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_PLL_CTRL_LN0_SD_STATE_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_PLL_CTRL_RESETVAL   (0x00000000u)

/* COMMA_LINK_DELAY */

#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE3_CDELAY_MASK (0xFF000000u)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE3_CDELAY_SHIFT (0x00000018u)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE3_CDELAY_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE2_CDELAY_MASK (0x00FF0000u)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE2_CDELAY_SHIFT (0x00000010u)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE2_CDELAY_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE1_CDELAY_MASK (0x0000FF00u)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE1_CDELAY_SHIFT (0x00000008u)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE1_CDELAY_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE0_CDELAY_MASK (0x000000FFu)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE0_CDELAY_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_LANE0_CDELAY_RESETVAL (0x00000000u)

#define CSL_WIZ8B8SB_COMMA_LINK_DELAY_RESETVAL (0x00000000u)

/* CMU_WAIT */

#define CSL_WIZ8B8SB_CMU_WAIT_WAIT_VAL_MASK (0x0001FFFFu)
#define CSL_WIZ8B8SB_CMU_WAIT_WAIT_VAL_SHIFT (0x00000000u)
#define CSL_WIZ8B8SB_CMU_WAIT_WAIT_VAL_RESETVAL (0x000124F8u)

#define CSL_WIZ8B8SB_CMU_WAIT_RESETVAL   (0x000124F8u)


#ifdef __cplusplus
}
#endif

#endif
